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* [ValueTracking] Extend r251146 to catch a fairly common caseJames Molloy2015-10-262-2/+35
| | | | | | | | | | | | | Even though we may not know the value of the shifter operand, it's possible we know the shifter operand is non-zero. This can allow us to infer more known bits - for example: %1 = load %p !range {1, 5} %2 = shl %q, %1 We don't know %1, but we do know that it is nonzero so %2[0] is known zero, and importantly %2 is known non-zero. Calling isKnownNonZero is nontrivially expensive so use an Optional to run it lazily and cache its result. llvm-svn: 251294
* [SCEV] Fix issues found during the review of r251283. NFC.Silviu Baranga2015-10-261-7/+8
| | | | | | | | | | | | | | | Summary: Replace (const SCEVAddRecExpr *) with cast<SCEVAddRecExpr>. Rename SCEVApplyRewriter to SCEVLoopAddRecRewriter (which is a more appropriate name) since the description is "takes a scalar evolution expression and applies the Map (Loop -> SCEV) to all AddRecExprs." Subscribers: llvm-commits, sanjoy Differential Revision: http://reviews.llvm.org/D14065 llvm-svn: 251292
* Loop Vectorizer - skipping "bitcast" before GEPElena Demikhovsky2015-10-263-89/+141
| | | | | | | | | | Vectorization of memory instruction (Load/Store) is possible when the pointer is coming from GEP. The GEP analysis allows to estimate the profit. In some cases we have a "bitcast" between GEP and memory instruction. I added code that skips the "bitcast". http://reviews.llvm.org/D13886 llvm-svn: 251291
* Tests: be slightly more specific to avoid conflict with path.Tim Northover2015-10-261-1/+1
| | | | llvm-svn: 251290
* fix test errors (on windows) for commit r251287Igor Breger2015-10-261-2/+2
| | | | llvm-svn: 251288
* AVX512: Enabled VPBROADCASTB lowering for v64i8 vectors.Igor Breger2015-10-262-96/+166
| | | | | | Differential Revision: http://reviews.llvm.org/D13896 llvm-svn: 251287
* [mips] Interrupt attribute support for mips32r2+.Vasileios Kalintiris2015-10-2617-13/+666
| | | | | | | | | | | | | | | | | | | Summary: This patch adds support for using the "interrupt" attribute on Mips for interrupt handling functions. At this time only mips32r2+ with the o32 ABI with the static relocation model is supported. Unsupported configurations will be rejected Patch by Simon Dardis (+ clang-format & some trivial changes to follow the LLVM coding standards by me). Reviewers: mpf, dsanders Subscribers: dsanders, vkalintiris, llvm-commits Differential Revision: http://reviews.llvm.org/D10768 llvm-svn: 251286
* AVX-512: Use correct extract vector length.Igor Breger2015-10-262-1/+12
| | | | | | | | Bug https://llvm.org/bugs/show_bug.cgi?id=25318 Differential Revision: http://reviews.llvm.org/D14062 llvm-svn: 251285
* [SCEV] Factor out common visiting patterns for SCEV rewriters. NFC.Silviu Baranga2015-10-261-93/+44
| | | | | | | | | | | | | | | | | Summary: Add a SCEVRewriteVisitor class which contains the common visiting patterns used when rewriting SCEVs. SCEVParameterRewriter and SCEVApplyRewriter now inherit from SCEVRewriteVisitor (and are therefore much simpler). Reviewers: anemet, mzolotukhin, sanjoy Subscribers: rengolin, llvm-commits, sanjoy Differential Revision: http://reviews.llvm.org/D13242 llvm-svn: 251283
* [InstCombine] Teach instcombine not to create extra PHI nodes when folding GEPsSilviu Baranga2015-10-262-1/+56
| | | | | | | | | | | | | | | | | | Summary: InstCombine tries to transform GEP(PHI(GEP1, GEP2, ..)) into GEP(GEP(PHI(...)) when possible. However, this may leave the old PHI node around. Even if we do end up folding the GEPs, having an extra PHI node might not be beneficial. This change makes the transformation more conservative. We now only do this if the PHI has only one use, and can therefore be removed after the transformation. Reviewers: jmolloy, majnemer Subscribers: mcrosier, mssimpso, llvm-commits Differential Revision: http://reviews.llvm.org/D13887 llvm-svn: 251281
* [ARM] Handle the inline asm constraint type 'o'James Molloy2015-10-263-0/+14
| | | | | | This means "memory with offset" and requires very little plumbing to get working. This fixes PR25317. llvm-svn: 251280
* Drop code after unreachable. No functionality change.Benjamin Kramer2015-10-262-3/+0
| | | | llvm-svn: 251278
* AVX512: Add AVX-512 not materializable instructions. Igor Breger2015-10-262-1/+63
| | | | | | | | | | Otherwise value can be reused , despite its value could be changed - produces incorrect assembler. https://llvm.org/bugs/show_bug.cgi?id=25270 Differential Revision: http://reviews.llvm.org/D14057 llvm-svn: 251275
* [Orc] Add license header to OrcTargetSupport.Lang Hames2015-10-261-1/+9
| | | | llvm-svn: 251274
* [Orc] In the CompileOnDemand layer, wrap module ownership in order to preserveLang Hames2015-10-261-19/+46
| | | | | | | | | | | | the module pointer type passed in by the user. The previous ownership scheme, where the user pointer was always moved into a std::shared_ptr, breaks if the user passes in a raw pointer. Discovered while working on the Orc C API, which should be landing shortly. I expect to include a test-case with that. llvm-svn: 251273
* Update test to take into account for r251271.David Majnemer2015-10-261-1/+1
| | | | llvm-svn: 251272
* [MC] Add support for GNU as-compatible binary operator precedenceDavid Majnemer2015-10-262-4/+88
| | | | | | | | | | GNU as and Darwin give the various binary operators different precedence. LLVM's MC supported the Darwin semantics but not the GNU semantics. This fixes PR25311. llvm-svn: 251271
* [MC] Don't crash when .word is given bogus valuesDavid Majnemer2015-10-263-2/+23
| | | | | | | | | | We didn't validate that the .word directive was given a sane value, leading to crashes when we attempt to write out the object file. Instead, perform some validation and issue a diagnostic pointing at the start of the diagnostic. llvm-svn: 251270
* RegionInfo: Correctly expand regionsTobias Grosser2015-10-251-14/+10
| | | | | | | | | | | | | | | | Instead of playing around with dominance to verify if the possible expansion of a scop region is indeed a single entry single exit region, we now distinguish two cases. In case we only append a basic block, all edges entering this basic block need to have come from within the region that is expanded. In case we join two regions, the source basic blocks of the edges that end at the entry node of the region that is appended most be part of either the original region or the region that is appended. This change will be tested through Polly. This fixes llvm.org/PR25242 llvm-svn: 251267
* Convert assert(false) into llvm_unreachable where it makes sense.Benjamin Kramer2015-10-256-10/+9
| | | | llvm-svn: 251266
* [X86][AVX] Regenerate tests.Simon Pilgrim2015-10-251-10/+10
| | | | llvm-svn: 251263
* docs: document `x` mangling in LangRefSaleem Abdulrasool2015-10-251-0/+2
| | | | | | | Windows has two different mangling specifiers. `x` is used on x86 for the `_` UserLabelPrefix. Others use `w` for the no UserLabelPrefix. llvm-svn: 251260
* [ScalarEvolution] Throw away dead code.Davide Italiano2015-10-251-17/+0
| | | | llvm-svn: 251256
* [ScalarEvolution] Get rid of NDEBUG in header (correctly this time).Davide Italiano2015-10-252-0/+10
| | | | llvm-svn: 251255
* [LCSSA] Unbreak build, don't reuse L; NFCSanjoy Das2015-10-251-2/+2
| | | | | | The build broke in r251248. llvm-svn: 251251
* [ScalarEvolution] Get rid of NDEBUG in header.Davide Italiano2015-10-252-13/+0
| | | | llvm-svn: 251249
* [LCSSA] Use range for loops; NFCSanjoy Das2015-10-251-28/+21
| | | | llvm-svn: 251248
* [X86][SSE4A] Fix for EXTRQI shuffle lowering.Simon Pilgrim2015-10-252-2/+25
| | | | | | Incorrect range test - found during fuzz testing. llvm-svn: 251245
* [X86][SSE] Refreshed tests (missing AVX512 patterns)Simon Pilgrim2015-10-251-0/+270
| | | | llvm-svn: 251238
* Scalarizer for masked.gather and masked.scatter intrinsics.Elena Demikhovsky2015-10-257-1/+401
| | | | | | | | | | When the target does not support these intrinsics they should be converted to a chain of scalar load or store operations. If the mask is not constant, the scalarizer will build a chain of conditional basic blocks. I added isLegalMaskedGather() isLegalMaskedScatter() APIs. Differential Revision: http://reviews.llvm.org/D13722 llvm-svn: 251237
* [X86][SSE] Added tests for shuffling through bitcasts.Simon Pilgrim2015-10-252-3/+103
| | | | llvm-svn: 251236
* [X86][SSE] vector sext/zext tests - remove unnecessary mcpu argumentsSimon Pilgrim2015-10-252-11/+11
| | | | llvm-svn: 251233
* [X86][SSE] shift/rotate tests - remove unnecessary mcpu arguments and ↵Simon Pilgrim2015-10-258-194/+194
| | | | | | regenerate/cleanup llvm-svn: 251232
* [X86] PMOV*X* tests - remove unnecessary mcpu arguments and regenerateSimon Pilgrim2015-10-251-38/+110
| | | | llvm-svn: 251230
* [X86] Stack folding tests - just use mtriple - no need for mcpu in these testsSimon Pilgrim2015-10-257-7/+7
| | | | llvm-svn: 251229
* [X86] Use correct calling convention for MCU psABI libcallsMichael Kuperstein2015-10-255-0/+48
| | | | | | | | | | | | When using the MCU psABI, compiler-generated library calls should pass some parameters in-register. However, since inreg marking for x86 is currently done by the front end, it will not be applied to backend-generated calls. This is a workaround for PR3997, which describes a similar issue for -mregparm. Differential Revision: http://reviews.llvm.org/D13977 llvm-svn: 251223
* [X86] Add support for elfiamcu tripleMichael Kuperstein2015-10-254-1/+15
| | | | | | | | This adds support for the i?86-*-elfiamcu triple, which indicates the IAMCU psABI is used. Differential Revision: http://reviews.llvm.org/D13977 llvm-svn: 251222
* Remove two unnecessary conversions from MVT to EVT. NFCCraig Topper2015-10-251-2/+2
| | | | llvm-svn: 251219
* Use MVT::SimpleValueType instead of MVT in template parameter. NFCCraig Topper2015-10-251-1/+2
| | | | llvm-svn: 251217
* Simplify boolean conditional return statements in tools/llvm-symbolizer.Rafael Espindola2015-10-241-3/+1
| | | | | | Patch by Richard. llvm-svn: 251216
* Simplify boolean expressions in tools/llvm-objdump.Rafael Espindola2015-10-241-2/+2
| | | | | | Patch by Richard. llvm-svn: 251215
* Refactor: Simplify boolean conditional return statements in lib/CodeGen.Rafael Espindola2015-10-249-60/+24
| | | | | | Patch by Richard. llvm-svn: 251213
* [X86][SSE] Use lowerVectorShuffleWithUNPCK instead of custom matches.Simon Pilgrim2015-10-245-128/+64
| | | | | | Most 128-bit and 256-bit shuffles were manually matching UNPCK patterns - use lowerVectorShuffleWithUNPCK to be more thorough. llvm-svn: 251211
* [Support] Add comment to explain why we can't drop NDEBUG.Davide Italiano2015-10-241-0/+5
| | | | | | Discussed with: Benjamin Kramer. llvm-svn: 251210
* [CodeGen] Get rid of NDEBUG to ensure structure stability.Davide Italiano2015-10-242-4/+0
| | | | | | | | | | | I think it's fine to keep this fields around in terms of overhead, I wasn't able to measure any substantial regression while running the test suite, but, in case this causes some regression I'm ready to revert and work on an alternative solution. This was tested building with clang/gcc both in Debug and Release mode and passes the test-suite. llvm-svn: 251209
* [X86][SSE] lowerVectorShuffleWithUNPCK - use equivalent shuffle mask test.Simon Pilgrim2015-10-241-25/+14
| | | | | | Use isShuffleEquivalent to match UNPCK shuffles - better support for build vector inputs. llvm-svn: 251207
* Refactor: Simplify boolean conditional return statements in ↵Michael Zolotukhin2015-10-242-11/+5
| | | | | | | | | | | | lib/Transforms/Vectorize (NFC). Summary: Use clang-tidy to simplify boolean conditional return statements Differential Revision: http://reviews.llvm.org/D10003 Patch by Richard<legalize@xmission.com> llvm-svn: 251206
* Removed old FIXME - we do generate movddup for SSE3 and higherSimon Pilgrim2015-10-241-2/+1
| | | | llvm-svn: 251205
* [DAGCombiner] Tidy up ConstantFP commutation. NFCISimon Pilgrim2015-10-241-37/+21
| | | | | | Move ConstantFP canonicalization of commutative instructions to start of 2-op node creation (matches integer) - simplifies constant folding code. llvm-svn: 251203
* Use all_of to simplify control flow. NFC.Benjamin Kramer2015-10-242-16/+4
| | | | llvm-svn: 251202
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