summaryrefslogtreecommitdiffstats
path: root/llvm
Commit message (Collapse)AuthorAgeFilesLines
* llvmc: Make 'true' and 'false' instances of a 'Bool' class.Mikhail Glushenkov2011-05-051-2/+5
| | | | llvm-svn: 130915
* llvmc: Make it possible to provide an argument to (join).Mikhail Glushenkov2011-05-051-9/+36
| | | | llvm-svn: 130914
* Update the gcov version used slightly, to make it stop causing modern gcov's toNick Lewycky2011-05-052-15/+35
| | | | | | crash. llvm-svn: 130911
* Remove dead function.Nick Lewycky2011-05-051-5/+0
| | | | llvm-svn: 130903
* When the path wasn't emitted by the frontend, discard any path on the sourceNick Lewycky2011-05-051-6/+11
| | | | | | filename. llvm-svn: 130897
* Disable physical register coalescing by default.Jakob Stoklund Olesen2011-05-041-1/+1
| | | | | | | | | | | | Joining physregs is inherently dangerous because it uses a heuristic to avoid creating invalid code. Linear scan had an emergency spilling mechanism to deal with those rare cases. The new greedy allocator does not. The greedy register allocator is much better at taking hints, so this has almost no impact on code size and quality. The few cases where it matters show up as unit tests that now have -join-physregs enabled explicitly. llvm-svn: 130896
* Set debug loc for new instructions.Devang Patel2011-05-041-3/+3
| | | | llvm-svn: 130895
* Set debug location for new PHI nodes created in exit block. Devang Patel2011-05-041-0/+2
| | | | llvm-svn: 130894
* Prepare remaining tests for -join-physreg going away.Jakob Stoklund Olesen2011-05-0415-34/+48
| | | | llvm-svn: 130893
* Fix X86RegisterInfo::getMatchingSuperRegClass for sub_8bit_hi.Jakob Stoklund Olesen2011-05-041-13/+8
| | | | | | | It is OK for B to be any GR8_ABCD_H superclass, the returned register class doesn't have to map surjectively onto B. llvm-svn: 130892
* Fix a batch of x86 tests to be coalescer independent.Jakob Stoklund Olesen2011-05-047-29/+38
| | | | | | | | Most of these tests require a single mov instruction that can come either before or after a 2-addr instruction. -join-physregs changes the behavior, but the results are equivalent. llvm-svn: 130891
* Document the automatic alias printing of InstAliases.Bill Wendling2011-05-041-0/+5
| | | | llvm-svn: 130889
* Add explicit 'unregister' method to CrashRecoveryConextCleanupRegistrar.Ted Kremenek2011-05-041-1/+6
| | | | llvm-svn: 130885
* Give this test an explicit register allocator, so that it can work even ifDan Gohman2011-05-041-1/+1
| | | | | | the default register allocator is changed. llvm-svn: 130883
* SjLj EH could produce a machine basic block that legitimately has more than oneBill Wendling2011-05-042-1/+102
| | | | | | | | | | | | | landing pad as its successor. SjLj exception handling jumps to the correct landing pad via a switch statement that's generated right before code-gen. Loosen the constraint in the machine instruction verifier to allow for this. Note, this isn't the most rigorous check since we cannot determine where that switch statement came from. But it's marginally better than turning this check off when SjLj exceptions are used. <rdar://problem/9187612> llvm-svn: 130881
* Preserve line number information while threading jumps.Devang Patel2011-05-041-2/+5
| | | | llvm-svn: 130880
* Create the parent directories to place the .gcda files in if they don't exist.Nick Lewycky2011-05-041-0/+18
| | | | | | | That's kinda weird because the .gcno files are supposed to already be there, but libgcov does this and somehow Google has managed to depend on it. llvm-svn: 130879
* Re-commit r130862 with a minor change to avoid an iterator running off the ↵Eli Friedman2011-05-043-29/+73
| | | | | | | | | | edge in some cases. Original message: Teach MachineCSE how to do simple cross-block CSE involving physregs. This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 . llvm-svn: 130877
* Preserve line number info.Devang Patel2011-05-041-1/+4
| | | | llvm-svn: 130876
* This test fails on ARM. The test shouldn't explicitly specify alignment (and ↵Galina Kistanova2011-05-041-4/+4
| | | | | | alignment 4 is wrong) and requires hard-float. llvm-svn: 130875
* If builder is initialized using an instruction as insertion point, then use ↵Devang Patel2011-05-041-0/+1
| | | | | | the instruction's debug location as current debug location. llvm-svn: 130874
* preserve line number info.Devang Patel2011-05-041-2/+3
| | | | llvm-svn: 130869
* Back out r130862; it appears to be breaking bootstrap.Eli Friedman2011-05-043-67/+29
| | | | llvm-svn: 130867
* Teach MachineCSE how to do simple cross-block CSE involving physregs. This ↵Eli Friedman2011-05-043-29/+67
| | | | | | allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 . llvm-svn: 130862
* Remove an unused variable.Duncan Sands2011-05-041-1/+0
| | | | llvm-svn: 130860
* Fix more register and coalescing dependencies.Jakob Stoklund Olesen2011-05-044-9/+7
| | | | llvm-svn: 130859
* Explicitly request physreg coalesing for a bunch of Thumb2 unit tests.Jakob Stoklund Olesen2011-05-047-7/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | These tests all follow the same pattern: mov r2, r0 movs r0, #0 $CMP r2, r1 it eq moveq r0, #1 bx lr The first 'mov' can be eliminated by rematerializing 'movs r0, #0' below the test instruction: $CMP r0, r1 mov.w r0, #0 it eq moveq r0, #1 bx lr So far, only physreg coalescing can do that. The register allocators won't yet split live ranges just to eliminate copies. They can learn, but this particular problem is not likely to show up in real code. It only appears because r0 is used for both the function argument and return value. llvm-svn: 130858
* Implement SystemZRegisterInfo::getMatchingSuperRegClass to enable ↵Jakob Stoklund Olesen2011-05-042-0/+18
| | | | | | cross-class joins. llvm-svn: 130857
* FileCheckize and break dependence on coalescing order.Jakob Stoklund Olesen2011-05-041-8/+6
| | | | llvm-svn: 130856
* Explicitly request -join-physregs for some tests that depend on it.Jakob Stoklund Olesen2011-05-042-2/+2
| | | | llvm-svn: 130855
* Do not emit location expression size twice.Devang Patel2011-05-042-12/+59
| | | | llvm-svn: 130854
* Fix cmake build.Rafael Espindola2011-05-041-0/+1
| | | | llvm-svn: 130850
* Remove LLVM IR metadata in test case committed in r130847.Akira Hatanaka2011-05-041-6/+3
| | | | llvm-svn: 130849
* Prevent instructions using $gp from being placed between a jalr and the ↵Akira Hatanaka2011-05-047-12/+125
| | | | | | instruction that restores the clobbered $gp. llvm-svn: 130847
* Producing a DW_FORM_addr for DW_AT_stmt_list is probably correct, butRafael Espindola2011-05-045-9/+28
| | | | | | | | | | | it is both inefficient and unexpected by dwarfdump. Change to a DW_FORM_data4. While in here, change the predicate name to reflect that the position is not really absolute (it is an offset), just that the linker needs a relocation. llvm-svn: 130846
* Rename -disable-physical-join to -join-physregs and invert it.Jakob Stoklund Olesen2011-05-041-4/+4
| | | | | | Physreg joining is still on by default, but I will turn it off shortly. llvm-svn: 130844
* Tighten up check for empty (i.e. no meaningful debug info) module. This ↵Devang Patel2011-05-041-15/+17
| | | | | | fixes dwarf-die2.c test case from gcc test suite. llvm-svn: 130842
* Add variations on: max(x,y) >= min(x,z) folds to true. This isn't that common,Duncan Sands2011-05-042-2/+134
| | | | | | | | but according to my super-optimizer there are only two missed simplifications of -instsimplify kind when compiling bzip2, and this is one of them. It amuses me to have bzip2 be perfectly optimized as far as instsimplify goes! llvm-svn: 130840
* Emit gcov data files to the directory specified in the metadata produced by theNick Lewycky2011-05-041-4/+23
| | | | | | frontend, if applicable. llvm-svn: 130835
* Fix crash when not setting GCOV_PREFIX.Nick Lewycky2011-05-041-1/+1
| | | | llvm-svn: 130834
* Remove dead intrinsics.Bill Wendling2011-05-041-16/+0
| | | | llvm-svn: 130831
* indvars: Added DisableIVRewrite and WidenIVs.Andrew Trick2011-05-042-9/+130
| | | | | | | | This adds functionality to remove size/zero extension during indvars without generating a canonical IV and rewriting all IV users. It's disabled by default so should have no effect on codegen. Work in progress. llvm-svn: 130829
* The system suppression file should catch these, but since they *once again* areNick Lewycky2011-05-042-0/+14
| | | | | | not, I'll just add them here and be done with it. llvm-svn: 130819
* Don't depend on the physreg coalescing order.Jakob Stoklund Olesen2011-05-042-5/+4
| | | | llvm-svn: 130818
* Don't run this test through -regalloc=basic.Jakob Stoklund Olesen2011-05-041-1/+0
| | | | | | | The basic allocator is really bad about hinting, so it doesn't eliminate all copies when physreg joining is disabled. llvm-svn: 130817
* Fix register-dependent XCore testsJakob Stoklund Olesen2011-05-041-6/+3
| | | | llvm-svn: 130816
* Fix register-dependent test in MSP430.Jakob Stoklund Olesen2011-05-041-1/+1
| | | | llvm-svn: 130815
* Implement MSP430RegisterInfo::getMatchingSuperRegClass to enable cross-classJakob Stoklund Olesen2011-05-041-0/+7
| | | | | | coalescing. llvm-svn: 130814
* Remove some random comments that snuck in from somewhere.Eric Christopher2011-05-041-4/+0
| | | | llvm-svn: 130812
* Mark ultra-super-registers QQQQ as call-clobbered instead of the D ↵Jakob Stoklund Olesen2011-05-033-32/+11
| | | | | | | | | | | | | | | sub-registers. LiveVariables doesn't understand that clobbering D0 and D1 completely overwrites Q0, so if Q0 is live-in to a function, its live range will extend beyond a function call that only clobbers D0 and D1. This shows up in the ARM/2009-11-01-NeonMoves test case. LiveVariables should probably implement the much stricter rules for physreg liveness that RAFast imposes - a physreg is killed by the first use of any alias. llvm-svn: 130801
OpenPOWER on IntegriCloud