summaryrefslogtreecommitdiffstats
path: root/llvm
Commit message (Collapse)AuthorAgeFilesLines
...
* AMDGPU/SI: Annotate Loops with Constant Condition in SIAnnotateControlFlow pass.Changpeng Fang2016-02-122-4/+34
| | | | | | | | | | | | | | | Summary: It is possible that the loop condition can be a boolean constant (infinite loop, for example). So we sould handle constant condition in annotating a loop. This patch adds this functionality to support annotating constant condition. Reviewers: tstellarAMD, arsenm Subscribers: llvm-commits, arsenm Differential Revision: http://reviews.llvm.org/D15093 llvm-svn: 260692
* [Hexagon] Remove HexagonExpandPredSpillCode passKrzysztof Parzyszek2016-02-123-203/+0
| | | | | | This code is dead. The expansion is now done in HexagonFrameLowering. llvm-svn: 260691
* [Hexagon] Eliminate pseudo instructions for circ/brev loads and storesKrzysztof Parzyszek2016-02-129-516/+228
| | | | | | | | | We can generate the actual instructions from the intrinsics without the need for pseudo-instructions. Also, since the intrinsics have a side- effect in a form of a store, attempt to optimize away loads from the store location. llvm-svn: 260690
* [AArch64] Reduce number of callee-save save/restores.Geoff Berry2016-02-125-145/+386
| | | | | | | | | | | | | | | | | | | | | Summary: Before this change, callee-save registers would be rounded up to even pairs of GPRs and FPRs. This change eliminates these extra padding load/stores, though it does keep the stack allocation the same size unless both the GPR and FPR sets have an odd size, in which case one full pair stack slot (16 bytes) is saved. This optimization cannot currently be done for MachO targets since they rely on a fast-path .debug_frame equivalent that can only encode callee-save registers as pairs. Reviewers: t.p.northover, rengolin, mcrosier, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17000 llvm-svn: 260689
* [Hexagon] Handle out-of-range offsets in eliminateFrameIndexKrzysztof Parzyszek2016-02-121-12/+15
| | | | | | | Create a virtual register that will hold the actual address and use it with the offset of 0 in the place of the original FI. llvm-svn: 260688
* [AArch64] Add support for Qualcomm Kryo CPU.Chad Rosier2016-02-1211-5/+2509
| | | | | | Machine model description by Dave Estes <cestes@codeaurora.org>. llvm-svn: 260686
* Delete the deprecated LLVMLinkModules.Rafael Espindola2016-02-125-77/+3
| | | | llvm-svn: 260683
* [AArch64] Merge two adjacent str WZR into str XZRJun Bum Lim2016-02-122-15/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change merges adjacent 32 bit zero stores into a 64 bit zero store. e.g., str wzr, [x0] str wzr, [x0, #4] becomes str xzr, [x0] Therefore, four adjacent 32 bit zero stores will be a single stp. e.g., str wzr, [x0] str wzr, [x0, #4] str wzr, [x0, #8] str wzr, [x0, #12] becomes stp xzr, xzr, [x0] Reviewers: mcrosier, jmolloy, gberry, t.p.northover Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D16933 llvm-svn: 260682
* [Hexagon] Specify vector alignment in DataLayout stringKrzysztof Parzyszek2016-02-122-7/+45
| | | | | | | | | | | The DataLayout can calculate alignment of vectors based on the alignment of the element type and the number of elements. In fact, it is the product of these two values. The problem is that for vectors of N x i1, this will return the alignment of N bytes, since the alignment of i1 is 8 bits. The vector types of vNi1 should be aligned to N bits instead. Provide explicit alignment for HVX vectors to avoid such complications. llvm-svn: 260678
* Fix uninitialized memory read.Benjamin Kramer2016-02-121-2/+2
| | | | | | Found by msan. llvm-svn: 260676
* [mips][micromips] Written missing test for CEIL.L.S, CEIL.L.D, FLOOR.L.S and ↵Hrvoje Varga2016-02-121-0/+4
| | | | | | | | FLOOR.L.D instructions Differential Revision: http://reviews.llvm.org/D17192 llvm-svn: 260673
* Remove LLVMGetTargetMachineData in go-binding.Haojian Wu2016-02-121-5/+0
| | | | | | | | | | | | | | | Summary: LLVMGetTargetMachineData has been removed, and LLVMGetDataLayout is suggested to use. The LLVMGetDataLayout is exposed in go bindings. So it's safe to remove the function. Reviewers: bkramer Subscribers: llvm-commits, axw Differential Revision: http://reviews.llvm.org/D17193 llvm-svn: 260670
* [attrs] Simplify the convergent removal to directly use the pre-builtChandler Carruth2016-02-121-22/+10
| | | | | | | | | | | | | | node set rather than walking the SCC directly. This directly exposes the functions and has already had null entries filtered out. We also don't need need to handle optnone as it has already been handled in the caller -- we never try to remove convergent when there are optnone functions in the SCC. With this change, the code for removing convergent should work with the new pass manager and a different SCC analysis. llvm-svn: 260668
* [attrs] Consolidate the test for a non-SCC, non-convergent function callChandler Carruth2016-02-121-20/+14
| | | | | | | | | | | | | | | | with the test for a non-convergent intrinsic call. While it is possible to use the call records to search for function calls, we're going to do an instruction scan anyways to find the intrinsics, we can handle both cases while scanning instructions. This will also make the logic more amenable to the new pass manager which doesn't use the same call graph structure. My next patch will remove use of CallGraphNode entirely and allow this code to work with both the old and new pass manager. Fortunately, it should also get strictly simpler without changing functionality. llvm-svn: 260666
* [unittests/ADT] OptionSetTest: ifdef out for now a specific test that fails ↵Argyrios Kyrtzidis2016-02-121-0/+4
| | | | | | on MSVC. llvm-svn: 260663
* AMDGPU: Set flat_scratch from flat_scratch_init regMatt Arsenault2016-02-1214-155/+142
| | | | | | | | | | | | | | This was hardcoded to the static private size, but this would be missing the offset and additional size for someday when we have dynamic sizing. Also stops always initializing flat_scratch even when unused. In the future we should stop emitting this unless flat instructions are used to access private memory. For example this will initialize it almost always on VI because flat is used for global access. llvm-svn: 260658
* C API: Remove LLVMGetDataLayout that was deprecated in 3.7Mehdi Amini2016-02-123-20/+2
| | | | | From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 260657
* Fix minor error with debug info doc.Mark Lacey2016-02-121-1/+1
| | | | | | Replace 'third' with 'fourth' in the description of the fourth argument. llvm-svn: 260656
* [unittests/ADT] OptionSetTest: ifdef out a part that fails to compile on MSVC.Argyrios Kyrtzidis2016-02-121-0/+3
| | | | llvm-svn: 260655
* [ADT] OptionSet: ifdef out some code that seems to be crashing MSVC.Argyrios Kyrtzidis2016-02-121-0/+3
| | | | llvm-svn: 260654
* [attrs] Run clang-format over a newly added routine in function-attrsChandler Carruth2016-02-121-12/+16
| | | | | | before I update it to be friendly with the new pass manager. llvm-svn: 260653
* [ADT] Introduce ‘OptionSet’ in llvm/ADT headers, which is a utility ↵Argyrios Kyrtzidis2016-02-123-0/+240
| | | | | | class that makes it convenient to work with enumerators representing bit options. llvm-svn: 260652
* AMDGPU: Set element_size in private resource descriptorMatt Arsenault2016-02-1211-12/+66
| | | | | | | | | Introduce a subtarget feature for this, and leave the default with the current behavior which assumes up to 16-byte loads/stores can be used. The field also seems to have the ability to be set to 2 bytes, but I'm not sure what that would be used for. llvm-svn: 260651
* [libFuzzer] make -runs=N flag also affect the simple runner (will execute ↵Kostya Serebryany2016-02-124-3/+28
| | | | | | every input N times) llvm-svn: 260649
* AMDGPU: Fix mishandling alignment when scalarizing vector loads/storesMatt Arsenault2016-02-121-2/+5
| | | | | | | I don't think this was causing any real problems, so I'm not sure how to test for this. llvm-svn: 260646
* AMDGPU: Initialize SILowerControlFlowMatt Arsenault2016-02-123-30/+43
| | | | llvm-svn: 260645
* AMDGPU: Remove trailing whitespaceMatt Arsenault2016-02-121-4/+4
| | | | llvm-svn: 260644
* Avoid linking LLVM component libraries with libLLVMAndrew Wilkins2016-02-124-24/+34
| | | | | | | | | | | Patch by Jack Howarth. When linking to libLLVM, don't also link to the component libraries that constitute libLLVM. Differential Revision: http://reviews.llvm.org/D16945 llvm-svn: 260641
* [msan] Put msan constructor in a comdat.Evgeniy Stepanov2016-02-125-18/+51
| | | | | | | | | | | | | | MSan adds a constructor to each translation unit that calls __msan_init, and does nothing else. The idea is to run __msan_init before any instrumented code. This results in multiple constructors and multiple .init_array entries in the final binary, one per translation unit. This is absolutely unnecessary; one would be enough. This change moves the constructors to a comdat group in order to drop the extra ones. llvm-svn: 260632
* [sancov] improved object files handling.Mike Aizatsky2016-02-128-109/+286
| | | | | | | | | | | | | | | | | | | Multi-dso programs result in multiple coverage files dumped of the form '<module_name>.<pid>.sancov'. When analyzing these coverage files it is important to use correct corresponding object file. This change removes the "-obj" sancov flag and lets user specify object file names alongside coverage files. Sancov tool would match them using <module_name> part of coverage file and short file name of the object file. Corresponding changes: - compiler-rt: http://reviews.llvm.org/D17171 - docs: http://reviews.llvm.org/D17175 Differential Revision: http://reviews.llvm.org/D17169 llvm-svn: 260628
* [LVI] Improve select handling to use conditionPhilip Reames2016-02-122-0/+68
| | | | | | | | | | This patches teaches LVI to recognize clamp idioms (e.g. select(a > 5, a, 5) will always produce something greater than 5. The tests end up being somewhat simplistic because trying to exercise the case I actually care about (a loop with a range check on a clamped secondary induction variable) ends up tripping across a couple of other imprecisions in the analysis. Ah, the joys of LVI... Differential Revision: http://reviews.llvm.org/D16827 llvm-svn: 260627
* AMDGPU: Quick fix for extreme slowness in spill-scavenge-offset.ll testNicolai Haehnle2016-02-121-6/+13
| | | | | | | | | | | | Summary: Also, some cosmetic fixes. Reviewers: arsenm, tstellarAMD Subscribers: qcolombet, llvm-commits Differential Revision: http://reviews.llvm.org/D17161 llvm-svn: 260625
* llvm/test/CodeGen/NVPTX/debug-file-loc.ll: Tweak expressions for dos path.NAKAMURA Takumi2016-02-111-2/+2
| | | | llvm-svn: 260623
* ARMv7k: use Cortex-A7 by default even for tvOSTim Northover2016-02-112-0/+13
| | | | | | Also actually test the default CPU from those triples. llvm-svn: 260621
* [codeview] Dump def range lengths in hexReid Kleckner2016-02-113-9/+9
| | | | | | | It makes it easier to correlate with assembly dumps, which are typically given with hex offsets. llvm-svn: 260619
* [SLP] Add debug output for extract cost (NFC)Matthew Simpson2016-02-111-4/+6
| | | | llvm-svn: 260614
* Re-apply r238452, the bug was in clang and was fixed in r260567.Quentin Colombet2016-02-114-7/+169
| | | | | | | | | | | | | | | | Original commit message: [InstCombine] Fold IntToPtr and PtrToInt into preceding loads. Currently we only fold a BitCast into a Load when the BitCast is its only user. Do the same for any no-op cast. Patch by Philip Pfaffe! Differential Revision: http://reviews.llvm.org/D9152 llvm-svn: 260612
* [libfuzzer] Removing coverage-related flags from asan options.Mike Aizatsky2016-02-111-3/+1
| | | | | | | | | | | Summary: Reasons to remove are twofold: - we don't really need coverage=1 for libfuzzer operation - makes controlling coverage for fuzzer processes non-trivial. Differential Revision: http://reviews.llvm.org/D17168 llvm-svn: 260611
* [x86] simplify getZeroVector() ; NFCISanjay Patel2016-02-111-39/+20
| | | | | | | | | | | Let DAG.getConstant() handle the splatting; there's no need to repeat that logic here. See also: http://reviews.llvm.org/rL258833 http://reviews.llvm.org/rL260582 llvm-svn: 260609
* Revert "Refactor the PassManagerBuilder: extract a ↵Mehdi Amini2016-02-112-78/+74
| | | | | | | | | | "addFunctionSimplificationPasses()"" This reverts commit r260603. I didn't intend to push it :( From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 260607
* Revert "Define the ThinLTO Pipeline"Mehdi Amini2016-02-112-46/+1
| | | | | | | | This reverts commit r260604. I didn't intend to push this now. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 260606
* Revert "Add a new insert_as() method to DenseMap and use it for ↵Mehdi Amini2016-02-112-61/+23
| | | | | | | | | | | | | ConstantUniqueMap" This reverts commit r260458. It was backported on an internal branch and broke stage2 build. Since this can lead to weird random crash I'm reverting upstream as well while investigating. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 260605
* Define the ThinLTO PipelineMehdi Amini2016-02-112-1/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: On the contrary to Full LTO, ThinLTO can afford to shift compile time from the frontend to the linker: both phases are parallel. This pipeline is based on the proposal in D13443 for full LTO. We ] didn't move forward on this proposal because the link was far too long after that. This patch refactor the "function simplification" passes that are part of the inliner loop in a helper function (this part is NFC and can be commited separately to simplify the diff). The ThinLTO pipeline integrates in the regular O2/O3 flow: - The compile phase perform the inliner with a somehow lighter function simplification. (TODO: tune the inliner thresholds here) This is intendend to simplify the IR and get rid of obvious things like linkonce_odr that will be inlined. - The link phase will run the pipeline from the start, extended with some specific passes that leverage the augmented knowledge we have during LTO. Especially after the inliner is done, a sequence of globalDCE/globalOpt is performed, followed by another run of the "function simplification" passes. The measurements on the public test suite as well as on our internal suite show an overall net improvement. The binary size for the clang executable is reduced by 5%. We're still tuning it with the bringup of ThinLTO but this should provide a good starting point. Reviewers: tejohnson Subscribers: joker.eph, llvm-commits, dexonsmith Differential Revision: http://reviews.llvm.org/D17115 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 260604
* Refactor the PassManagerBuilder: extract a "addFunctionSimplificationPasses()"Mehdi Amini2016-02-112-74/+78
| | | | | | | | It is intended to contains the passes run over a function after the inliner is done with a function and before it moves to its callers. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 260603
* [IRTranslator] Use a single virtual register to represent any Value.Quentin Colombet2016-02-113-30/+21
| | | | | | PR26161. llvm-svn: 260602
* [AArch64] Implements the lowering of formal arguments for GlobalISel.Quentin Colombet2016-02-112-0/+53
| | | | | | | | | | | | | | | | This is just a trivial implementation: - Support only arguments passed in registers. - Support only "plain" arguments, i.e., no sext/zext attribute. At this point, it is possible to play with the IRTranslator on AArch64: llc -mtriple arm64-<vendor>-<os> -print-machineinstrs <input.ll> -o - -global-isel For now, we only support the translation of program with adds and returns. Follow-up patches are on their way to add a test case (the MIRParser is not ready as it is). llvm-svn: 260600
* AMDGPU/SI: Make sure MIMG descriptors and samplers stay in SGPRsTom Stellard2016-02-117-0/+150
| | | | | | | | | | | | | | | | Summary: It's possible to have resource descriptors and samplers stored in VGPRs, either by a VMEM instruction or in the case of samplers, floating-point calculations. When this happens, we need to use v_readfirstlane to copy these values back to sgprs. Reviewers: mareko, arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D17102 llvm-svn: 260599
* Add support for phi nodes in the LLVM C API testAmaury Sechet2016-02-114-18/+67
| | | | | | | | | | | | Summary: This required to add binding to Instruction::removeFromParent so that instruction can be forward declared and then moved at the right place. Reviewers: bogner, chandlerc, echristo, dblaikie, joker.eph, Wallbraker Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D17057 llvm-svn: 260597
* [GlobalISel][MachineIRBuilder] Fix comments.Quentin Colombet2016-02-111-1/+2
| | | | llvm-svn: 260594
* [GlobalISel] Make the getter for MBB in MachneIRBuilder public.Quentin Colombet2016-02-111-5/+6
| | | | llvm-svn: 260593
OpenPOWER on IntegriCloud