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* LTO: add API to set strategy for -internalizeDuncan P. N. Exon Smith2014-01-146-22/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add API to LTOCodeGenerator to specify a strategy for the -internalize pass. This is a new attempt at Bill's change in r185882, which he reverted in r188029 due to problems with the gold linker. This puts the onus on the linker to decide whether (and what) to internalize. In particular, running internalize before outputting an object file may change a 'weak' symbol into an internal one, even though that symbol could be needed by an external object file --- e.g., with arclite. This patch enables three strategies: - LTO_INTERNALIZE_FULL: the default (and the old behaviour). - LTO_INTERNALIZE_NONE: skip -internalize. - LTO_INTERNALIZE_HIDDEN: only -internalize symbols with hidden visibility. LTO_INTERNALIZE_FULL should be used when linking an executable. Outputting an object file (e.g., via ld -r) is more complicated, and depends on whether hidden symbols should be internalized. E.g., for ld -r, LTO_INTERNALIZE_NONE can be used when -keep_private_externs, and LTO_INTERNALIZE_HIDDEN can be used otherwise. However, LTO_INTERNALIZE_FULL is inappropriate, since the output object file will eventually need to link with others. lto_codegen_set_internalize_strategy() sets the strategy for subsequent calls to lto_codegen_write_merged_modules() and lto_codegen_compile*(). <rdar://problem/14334895> llvm-svn: 199191
* Always let value types influence register classes.Jakob Stoklund Olesen2014-01-142-4/+38
| | | | | | | | | | | | | | | | | | | | | When creating a virtual register for a def, the value type should be used to pick the register class. If we only use the register class constraint on the instruction, we might pick a too large register class. Some registers can store values of different sizes. For example, the x86 xmm registers can hold f32, f64, and 128-bit vectors. The three different value sizes are represented by register classes with identical register sets: FR32, FR64, and VR128. These register classes have different spill slot sizes, so it is important to use the right one. The register class constraint on an instruction doesn't necessarily care about the size of the value its defining. The value type determines that. This fixes a problem where InstrEmitter was picking 32-bit register classes for 64-bit values on SPARC. llvm-svn: 199187
* Switch the NEON register class from QPR to DPair.Jakob Stoklund Olesen2014-01-141-1/+1
| | | | | | | | | | | | | The already allocatable DPair superclass contains odd-even D register pair in addition to the even-odd pairs in the QPR register class. There is no reason to constrain the set of D register pairs that can be used for NEON values. Any NEON instructions that require a Q register will automatically constrain the register class to QPR. The allocation order for DPair begins with the QPR registers, so register allocation is unlikely to change much. llvm-svn: 199186
* [PM] Fix stale header blocker, found by Duncan Smith in code review!Chandler Carruth2014-01-141-2/+2
| | | | llvm-svn: 199185
* Remove the last weird subproject, 'privbracket'.Chandler Carruth2014-01-142-5/+1
| | | | llvm-svn: 199183
* Add checks to configure for sufficiently modern host compilers. ThisChandler Carruth2014-01-142-1/+401
| | | | | | | | | | | requires Clang 3.1 or GCC 4.7. If the compiler isn't Clang or GCC, we don't try to do any sanity checking, but this give us at least a reasonable baseline of modern compilers. Also, I'm not claiming that this is the best way to do compiler version tests. I'm happy for anyone to suggest better ways of doing this test. llvm-svn: 199182
* Replace .mips_hack_stocg with ".set micromips" and ".set nomicromips".Rafael Espindola2014-01-148-61/+67
| | | | | | | This matches what gnu as does and implementing this is easier than arguing about it. llvm-svn: 199181
* Fix llc to not reuse spill slots in functions that invoke setjmp()Mark Seaborn2014-01-142-4/+143
| | | | | | | | | | | | | | | | | | We need to ensure that StackSlotColoring.cpp does not reuse stack spill slots in functions that call "returns_twice" functions such as setjmp(), otherwise this can lead to miscompiled code, because a stack slot would be clobbered when it's still live. This was already handled correctly for functions that call setjmp() (though this wasn't covered by a test), but not for functions that invoke setjmp(). We fix this by changing callsFunctionThatReturnsTwice() to check for invoke instructions. This fixes PR18244. llvm-svn: 199180
* Ok, really, for the last time, llvm-gcc is dead Jim.Chandler Carruth2014-01-142-35/+2
| | | | | | | | | Also, so is stacker, llvm-tv, etc. Wow. But will someone please fess up to what projects/privbracket is and why our autoconf build supports it? llvm-svn: 199179
* llvm-gcc is dead. REALLY. IT'S DEAD JIM.Chandler Carruth2014-01-142-6/+6
| | | | llvm-svn: 199178
* Make getTargetStreamer return a possibly null pointer.Rafael Espindola2014-01-149-12/+12
| | | | | | | | | This will allow it to be called from target independent parts of the main streamer that don't know if there is a registered target streamer or not. This in turn will allow targets to perform extra actions at specified points in the interface: add extra flags for some labels, extra work during finalization, etc. llvm-svn: 199174
* Remove extra } in documentation commentDuncan P. N. Exon Smith2014-01-131-2/+0
| | | | llvm-svn: 199162
* Clean up RUN command for Assembler/getInt.ll.Cameron McInally2014-01-131-2/+1
| | | | llvm-svn: 199158
* Factor the option and checking of compiler version better. Put theChandler Carruth2014-01-133-19/+19
| | | | | | | | option with the others in the top level CMakeLists, and put the check in HandleLLVMOptions. This will also let it be used from the standalone Clang builds. llvm-svn: 199149
* Raise the minimum CMake version to 2.8.8 -- we have a report that theChandler Carruth2014-01-131-1/+1
| | | | | | | | | | | | | compiler version checking doesn't work on 2.8.7. This feature was documented in 2.8.10, but existed for an unknown amount of time before that. I'm actually happy to revert this and remove the use of the feature if there is anyone with a specific problem updating CMake. Please just let me know. I don't want to re-implement this CMake functionality unless there is a reason, and this is the only real way to find that out. llvm-svn: 199148
* Fix uninitialized warning in llvm/lib/IR/DataLayout.cpp.Cameron McInally2014-01-132-2/+7
| | | | llvm-svn: 199147
* [DAG] Refactor ReassociateOps - no functional change intended.Juergen Ributzka2014-01-131-73/+44
| | | | llvm-svn: 199146
* Add a check that the host compiler is modern to CMake, take 1. This isChandler Carruth2014-01-131-0/+19
| | | | | | | | | | | | | likely to be reverted and re-applied a few times. The minimum versions we're aiming at: GCC 4.7 Clang 3.1 MSVC 17.0 (Visual Studio 2012) Let me know if something breaks! llvm-svn: 199145
* [DAG] Teach DAG to also reassociate vector operationsJuergen Ributzka2014-01-134-27/+82
| | | | | | | | | | This commit teaches DAG to reassociate vector ops, which in turn enables constant folding of vector op chains that appear later on during custom lowering and DAG combine. Reviewed by Andrea Di Biagio llvm-svn: 199135
* Hide the pre-RA-sched= option.Andrew Trick2014-01-132-2/+2
| | | | | | | | | This is a very confusing option for a feature that will go away. -enable-misched is exposed instead to help triage issues with the new scheduler. llvm-svn: 199133
* Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocksWeiming Zhao2014-01-132-0/+25
| | | | | | | | | The issue is caused when Post-RA scheduler reorders a bundle instruction (IT block). However, it only flips the CPSR liveness of the bundle instruction, leaves the instructions inside the bundle unchanged, which causes inconstancy and crashes Thumb2SizeReduction.cpp::ReduceMBB(). llvm-svn: 199127
* Update getLazyBitcodeModule to use ErrorOr for error handling.Rafael Espindola2014-01-137-34/+41
| | | | llvm-svn: 199125
* [AArch64] Fix assertion failure caused by an invalid comparison between ↵Andrea Di Biagio2014-01-132-2/+32
| | | | | | | | | | | | | APInt values. APInt only knows how to compare values with the same BitWidth and asserts in all other cases. With this fix, function PerformORCombine does not use the APInt equality operator if the APInt values returned by 'isConstantSplat' differ in BitWidth. In that case they are different and no comparison is needed. llvm-svn: 199119
* Fix indentation.Joerg Sonnenberger2014-01-131-11/+11
| | | | llvm-svn: 199118
* [SystemZ] Flesh out stackrestore test (frame-11.ll)Richard Sandiford2014-01-131-3/+10
| | | | | | ...so that it does something vaguely sensible. llvm-svn: 199117
* [SystemZ] Add "volatile" to a dead store in variable-loc.llRichard Sandiford2014-01-131-2/+2
| | | | llvm-svn: 199116
* [SystemZ] Improve risbg-01.ll testRichard Sandiford2014-01-131-6/+5
| | | | | | | | | | | | | | The old mask in f24 wasn't well chosen because the lshr would always be zero. CodeGen didn't detect this but InstCombine would. The new mask ensures that both shifts are needed. f26 is specifically testing for a wrap-around mask. The AND can be applied to just the shift left, either before or after the shift. Again, CodeGen kept it in the original form but InstCombine would mask after the shift instead. The exact choice of NILF isn't important for the test so I just dropped it and kept the rotate. llvm-svn: 199115
* [SystemZ] Optimize (sext (ashr (shl ...), ...))Richard Sandiford2014-01-133-3/+52
| | | | | | | | | | ...into (ashr (shl (anyext X), ...), ...), which requires one fewer instruction. The (anyext X) can sometimes be simplified too. I didn't do this in DAGCombiner because widening shifts isn't a win on all targets. llvm-svn: 199114
* fix a -Wdocumentation warning.Chris Lattner2014-01-131-1/+1
| | | | llvm-svn: 199113
* ARM: add test for r199108. Oops.Tim Northover2014-01-131-0/+15
| | | | | | rdar://problem/15800156 llvm-svn: 199109
* ARM: constrain Thumb LDRLIT pseudo-instructions to r0-r7.Tim Northover2014-01-131-4/+5
| | | | | | | | | | | | Previously we only used GPR for the destination placeholder in "ldr rD, [pc, incorrect codegen under the integrated assembler. This should fix both issues (which probably only affect MachO targets at the moment). rdar://problem/15800156 llvm-svn: 199108
* [x86] Fix retq/retl handling in 64-bit modeDavid Woodhouse2014-01-136-11/+110
| | | | | | | | | | | | | | | | | | | | | | | | | This finishes the job started in r198756, and creates separate opcodes for 64-bit vs. 32-bit versions of the rest of the RET instructions too. LRETL/LRETQ are interesting... I can't see any justification for their existence in the SDM. There should be no 'LRETL' in 64-bit mode, and no need for a REX.W prefix for LRETQ. But this is what GAS does, and my Sandybridge CPU and an Opteron 6376 concur when tested as follows: asm __volatile__("pushq $0x1234\nmovq $0x33,%rax\nsalq $32,%rax\norq $1f,%rax\npushq %rax\nlretl $8\n1:"); asm __volatile__("pushq $1234\npushq $0x33\npushq $1f\nlretq $8\n1:"); asm __volatile__("pushq $0x33\npushq $1f\nlretq\n1:"); asm __volatile__("pushq $0x1234\npushq $0x33\npushq $1f\nlretq $8\n1:"); cf. PR8592 and commit r118903, which added LRETQ. I only added LRETIQ to match it. I don't quite understand how the Intel syntax parsing for ret instructions is working, despite r154468 allegedly fixing it. Aren't the explicitly sized 'retw', 'retd' and 'retq' supposed to work? I have at least made the 'lretq' work with (and indeed *require*) the 'q'. llvm-svn: 199106
* [PM] Split DominatorTree into a concrete analysis result object whichChandler Carruth2014-01-1360-362/+351
| | | | | | | | | | | | | | | | | | | | | | | can be used by both the new pass manager and the old. This removes it from any of the virtual mess of the pass interfaces and lets it derive cleanly from the DominatorTreeBase<> template. In turn, tons of boilerplate interface can be nuked and it turns into a very straightforward extension of the base DominatorTree interface. The old analysis pass is now a simple wrapper. The names and style of this split should match the split between CallGraph and CallGraphWrapperPass. All of the users of DominatorTree have been updated to match using many of the same tricks as with CallGraph. The goal is that the common type remains the resulting DominatorTree rather than the pass. This will make subsequent work toward the new pass manager significantly easier. Also in numerous places things became cleaner because I switched from re-running the pass (!!! mid way through some other passes run!!!) to directly recomputing the domtree. llvm-svn: 199104
* [PM][cleanup] Clean up comments and use modern doxygen in this file.Chandler Carruth2014-01-131-31/+33
| | | | | | | This is a precursor to breaking the pass that computes the DominatorTree apart from the concrete DominatorTree. llvm-svn: 199103
* AVX-512: Embedded Rounding Control - encoding and printingElena Demikhovsky2014-01-1310-234/+338
| | | | | | Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC. llvm-svn: 199102
* [PM] Fix the const-correctness of the generic DominatorTreeBase toChandler Carruth2014-01-131-16/+16
| | | | | | | | | | | | | | | | | support notionally const queries even though they may trigger DFS numbering updates. The updating of DFS numbers and tracking of slow queries do not mutate the observable state of the domtree. They should be const to differentiate them from the APIs which mutate the tree directly to do incremental updates. This will make it possible in a world where the DominatorTree is not a pass but merely the result of running a pass to derive DominatorTree from the base class as it was originally designed, removing a huge duplication of API in DominatorTree. llvm-svn: 199101
* [PM] Pull the generic graph algorithms and data structures for dominatorChandler Carruth2014-01-1310-719/+751
| | | | | | | | | | | | | | | | | | | | | | | | | trees into the Support library. These are all expressed in terms of the generic GraphTraits and CFG, with no reliance on any concrete IR types. Putting them in support clarifies that and makes the fact that the static analyzer in Clang uses them much more sane. When moving the Dominators.h file into the IR library I claimed that this was the right home for it but not something I planned to work on. Oops. So why am I doing this? It happens to be one step toward breaking the requirement that IR verification can only be performed from inside of a pass context, which completely blocks the implementation of verification for the new pass manager infrastructure. Fixing it will also allow removing the concept of the "preverify" step (WTF???) and allow the verifier to cleanly flag functions which fail verification in a way that precludes even computing dominance information. Currently, that results in a fatal error even when you ask the verifier to not fatally error. It's awesome like that. The yak shaving will continue... llvm-svn: 199095
* Revert "ReMat: fix overly cavalier attitude to sub-register indices"Tim Northover2014-01-131-4/+24
| | | | | | | | | | Very sorry, this was a premature patch that I still need to investigate and finish off (for some reason beyond me at the moment it doesn't actually fix the issue in all cases). This reverts commit r199091. llvm-svn: 199093
* Docs: fix sign of division and increase equivocation on code generated.Tim Northover2014-01-131-5/+5
| | | | | | I should have been a politician. llvm-svn: 199092
* ReMat: fix overly cavalier attitude to sub-register indicesTim Northover2014-01-131-24/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two attempted optimisations in reMaterializeTrivialDef, trying to avoid promoting the size of a register too much when rematerializing. Unfortunately, both appear to be flawed. First, we see if the original register would have worked, but this is inadequate. Consider: v1 = SOMETHING (v1 is QQ) v2:Q0 = COPY v1:Q1 (v1, v2 are QQ) ... uses of v2 In this case even though v2 *could* be used directly as the output of SOMETHING, this would set the wrong bits of the QQ register involved. The correct rematerialization must be: v2:Q0_Q1 = SOMETHING (v2 promoted to QQQ) ... uses of v2:Q1_Q2 For the second optimisation, if the correct remat is "v2:idx = SOMETHING" then we can't necessarily expect v2 itself to be valid for SOMETHING, but we do try to hunt for a class between v1 and v2 that works. Unfortunately, this is also wrong: v1 = SOMETHING (v1 is QQ) v2:Q0_Q1 = COPY v1 (v1 is QQ, v2 is QQQ) ... uses of v2 as a QQQ The canonical rematerialization here is "v2:Q0_Q1 = SOMETHING". However current logic would decide that v2 could be a QQ (no interest is taken in later uses). This patch, therefore, always accepts the widened register class without trying to be clever. Generally there is no penalty to this (e.g. in the common GR32 < GR64 case, expanding the width doesn't matter because it's not like you were going to do anything else with the high bits of a GR32 register). It can increase register pressure in cases like the ARM VFP regs though (multiple non-overlapping but equivalent subregisters). Hopefully this situation is rare enough that it won't matter. Unfortunately, no in-tree targets actually expose this as far as I can tell (there are so few isAsCheapAsAMove instructions for it to trigger on) so I've been unable to produce a test. It was exposed in our ARM64 SPEC tests though, and I will be adding a test there that we should be able to contribute soon(TM). llvm-svn: 199091
* [cleanup] Re-sort the examples #include lines with my sort_includesChandler Carruth2014-01-1311-14/+14
| | | | | | script. llvm-svn: 199089
* [cleanup] Fix the includes in the examples for r199082.Chandler Carruth2014-01-1314-14/+14
| | | | llvm-svn: 199087
* [cleanup] Switch comments to use '\brief' style instead of '@brief'Chandler Carruth2014-01-131-18/+12
| | | | | | | | style, and remove some unnecessary comments (the code is perfectly self-documenting here). Also clang-format the function declarations as they wrap cleanly now. llvm-svn: 199084
* [cleanup] Move the Dominators.h and Verifier.h headers into the IRChandler Carruth2014-01-1391-107/+107
| | | | | | | | | | | | | | | | | | directory. These passes are already defined in the IR library, and it doesn't make any sense to have the headers in Analysis. Long term, I think there is going to be a much better way to divide these matters. The dominators code should be fully separated into the abstract graph algorithm and have that put in Support where it becomes obvious that evn Clang's CFGBlock's can use it. Then the verifier can manually construct dominance information from the Support-driven interface while the Analysis library can provide a pass which both caches, reconstructs, and supports a nice update API. But those are very long term, and so I don't want to leave the really confusing structure until that day arrives. llvm-svn: 199082
* [cleanup] Add a missing include exposed by resorting other includes.Chandler Carruth2014-01-131-0/+1
| | | | | | Should fix the build. llvm-svn: 199081
* Re-sort #include lines again, prior to moving headers around.Chandler Carruth2014-01-1321-40/+22
| | | | llvm-svn: 199080
* [PM] Wire up support for writing bitcode with new PM.Chandler Carruth2014-01-137-10/+70
| | | | | | | | | | This moves the old pass creation functionality to its own header and updates the callers of that routine. Then it adds a new PM supporting bitcode writer to the header file, and wires that up in the opt tool. A test is added that round-trips code into bitcode and back out using the new pass manager. llvm-svn: 199078
* llvm/test/ExecutionEngine/MCJIT/load-object-a.ll: Put together rm(1) and ↵NAKAMURA Takumi2014-01-131-7/+2
| | | | | | mkdir(1) at the top. llvm-svn: 199077
* [CMake] Move BUG_REPORT_URL from clang to llvm.NAKAMURA Takumi2014-01-131-0/+3
| | | | | | | | | | It was too late to set BUG_REPORT_URL after configure_file(config.h). BUG_REPORT_URL in config.h.cmake would be updated at 2nd run of cmake. It caused many recompilations. FYI, configure handles BUG_REPORT_URL in llvm side. llvm-svn: 199076
* [PM] Wire up support for printing assembly output from the opt command.Chandler Carruth2014-01-132-3/+22
| | | | | | This lets us round-trip IR in the expected manner with the opt tool. llvm-svn: 199075
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