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* Revert rL315894, "SLPVectorizer.cpp: Try to appease stage2-3 difference. ↵NAKAMURA Takumi2017-10-162-162/+23
| | | | | | (D38586)" llvm-svn: 315896
* Move folding of icmp with zero after checking for min/max idioms.Nikolai Bozhenov2017-10-163-12/+24
| | | | | | | | | | | | | | | | | | | | | Summary: The following transformation for cmp instruction: icmp smin(x, PositiveValue), 0 -> icmp x, 0 should only be done after checking for min/max to prevent infinite looping caused by a reverse canonicalization. That is why this transformation was moved to place after the mentioned check. Reviewers: spatel, efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38934 Patch by: Artur Gainullin <artur.gainullin@intel.com> llvm-svn: 315895
* SLPVectorizer.cpp: Try to appease stage2-3 difference. (D38586)NAKAMURA Takumi2017-10-162-23/+162
| | | | llvm-svn: 315894
* [TableGen] Range loopify DAGISelMatcher. NFC.Javed Absar2017-10-161-15/+15
| | | | llvm-svn: 315891
* [aarch64][globalisel] Fix a crash in selectAddrModeIndexed() caused by ↵Daniel Sanders2017-10-161-1/+5
| | | | | | | | | | incorrect G_FRAME_INDEX handling The wrong operand was being rendered to the result instruction. The crash was detected by Bitcode/simd_ops/AArch64_halide_runtime.bc llvm-svn: 315890
* bpf: fix bug on silently truncating 64-bit immediateYonghong Song2017-10-163-3/+42
| | | | | | | | | | | | | | | | We came across an llvm bug when compiling some testcases that 64-bit immediates are silently truncated into 32-bit and then packed into BPF_JMP | BPF_K encoding. This caused comparison with wrong value. This bug looks to be introduced by r308080. The Select_Ri pattern is supposed to be lowered into J*_Ri while the latter only support 32-bit immediate encoding, therefore Select_Ri should have similar immediate predicate check as what J*_Ri are doing. Reported-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 315889
* [PowerPC] Eliminate sign- and zero-extensions if already sign- or zero-extendedHiroshi Inoue2017-10-1610-62/+510
| | | | | | | | | | | | | | | | | | This patch enables redundant sign- and zero-extension elimination in PowerPC MI Peephole pass. If the input value of a sign- or zero-extension is known to be already sign- or zero-extended, the operation is redundant and can be eliminated. One common case is sign-extensions for a method parameter or for a method return value; they must be sign- or zero-extended as defined in PPC ELF ABI. For example of the following simple code, two extsw instructions are generated before the invocation of int_func and before the return. With this patch, both extsw are eliminated. void int_func(int); void ii_test(int a) { if (a & 1) return int_func(a); } Such redundant sign- or zero-extensions are quite common in many programs; e.g. I observed about 60,000 occurrences of the elimination while compiling the LLVM+CLANG. Differential Revision: https://reviews.llvm.org/D31319 llvm-svn: 315888
* Re-commit r315885: [globalisel][tblgen] Add support for iPTR and implement ↵Daniel Sanders2017-10-168-25/+229
| | | | | | | | | | | | | | | | | | | | | | | | | | | am_unscaled* and am_indexed* Summary: iPTR is a pointer of subtarget-specific size to any address space. Therefore type checks on this size derive the SizeInBits from a subtarget hook. At this point, we can import the simplests G_LOAD rules and select load instructions using them. Further patches will support for the predicates to enable additional loads as well as the stores. The previous commit failed on MSVC due to a failure to convert an initializer_list to a std::vector. Hopefully, MSVC will accept this version. Depends on D37457 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37458 llvm-svn: 315887
* Revert r315885: [globalisel][tblgen] Add support for iPTR and implement ↵Daniel Sanders2017-10-167-205/+11
| | | | | | | | am_unscaled* and am_indexed* MSVC doesn't like one of the constructors. llvm-svn: 315886
* [globalisel][tblgen] Add support for iPTR and implement am_unscaled* and ↵Daniel Sanders2017-10-167-11/+205
| | | | | | | | | | | | | | | | | | | | | | | | am_indexed* Summary: iPTR is a pointer of subtarget-specific size to any address space. Therefore type checks on this size derive the SizeInBits from a subtarget hook. At this point, we can import the simplests G_LOAD rules and select load instructions using them. Further patches will support for the predicates to enable additional loads as well as the stores. Depends on D37457 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37458 llvm-svn: 315885
* [globalisel][tablegen] Implement unindexed load, non-extending load, and ↵Daniel Sanders2017-10-165-20/+177
| | | | | | | | | | | | | | | | | | | | | | | | MemVT checks Summary: This includes some context-sensitivity in the MVT to LLT conversion so that pointer types are tested correctly. FIXME: I'm not happy with the way this is done since everything is a special-case. I've yet to find a reasonable way to implement it. select-load.mir fails because <1 x s64> loads in tablegen get priority over s64 loads. This is fixed in the next patch and as such they should be committed together, I've posted them separately to help with the review. Depends on D37456 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37457 llvm-svn: 315884
* [Hexagon] Add LLVM_ATTRIBUTE_UNUSED to operator<<, NFCKrzysztof Parzyszek2017-10-161-0/+8
| | | | | | This should silence "unused function" warnings. llvm-svn: 315883
* Search for libxml2 on macOS too.Nico Weber2017-10-151-1/+1
| | | | | | | | This allows lld-link to process /manifestinput: flags on macOS too. Also makes the `REQUIRES: manifesttool` lld tests run on macOS. Setting LLVM_ENABLE_LIBXML2 to off can suppress this behavior, like on Linux. llvm-svn: 315873
* [tablegen] Use hasPredCode()/hasImmCode() instead of ↵Daniel Sanders2017-10-152-5/+17
| | | | | | | | getPredCode().empty()/getImmCode().empty(). NFC These are cheaper ways of testing for the presence of code than generating the C++ code and testing it's empty. llvm-svn: 315872
* Phony change to CMakeLists.txt to (hopefully) trigger regenerationKrzysztof Parzyszek2017-10-151-0/+1
| | | | | | | Ninja doesn't seem to recognize a change in a CMakeLists.txt in a subdirectory, so r315861 is not having any effect. llvm-svn: 315870
* Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as ↵Daniel Sanders2017-10-156-53/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
* Revert r315863: [globalisel][tablegen] Import ComplexPattern when used as an ↵Daniel Sanders2017-10-156-159/+53
| | | | | | | | operator A large number of bots are failing on an ambiguous constructor call. llvm-svn: 315866
* [globalisel][tablegen] Import ComplexPattern when used as an operatorDaniel Sanders2017-10-156-53/+159
| | | | | | | | | | | | | | | | | | | | | | | Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315863
* [X86] Remove the SlowBTMem feature flag entirelyCraig Topper2017-10-154-66/+31
| | | | | | Turns out we have no patterns on the instructions that were using this feature flag for other reasons. These instructions are slow on all modern CPUs so it seems unlikely that we will spend any effort supporting these instructions going forward. So we might as well just kill of the feature flag and just fix up the comments. llvm-svn: 315862
* [unittests] Only build llvm-cfi-verify if X86 is in LLVM_TARGETS_TO_BUILDKrzysztof Parzyszek2017-10-151-1/+4
| | | | | | | The test requires a target for triple x86-64, and it fails in builds that do not have the X86 backend. llvm-svn: 315861
* [AVX512] Don't mark EXTLOAD as legal with AVX512. Continue using custom ↵Craig Topper2017-10-156-238/+81
| | | | | | | | | | | | | | | | | | | lowering. Summary: This was impeding our ability to combine the extending shuffles with other shuffles as you can see from the test changes. There's one special case that needed to be added to use VZEXT directly for v8i8->v8i64 since the custom lowering requires v64i8. Reviewers: RKSimon, zvi, delena Reviewed By: delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38714 llvm-svn: 315860
* [X86] Add FeatureSlowBTMem to Haswell, Broadwell, Skylake, Cannonlake, and ↵Craig Topper2017-10-151-6/+13
| | | | | | | | | | | | | | | | Knights Landing CPUs. Summary: I see nothing in Agner Fog's tables to indicate that this improved between Ivy Bridge and Haswell. It's also set for all Atom CPUs so I assume KNL should have it too. Reviewers: RKSimon, zvi, gadi.haber Reviewed By: gadi.haber Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38890 llvm-svn: 315859
* [TableGen] Remove error checks incorrectly failing on non-error conditionsKrzysztof Parzyszek2017-10-151-49/+6
| | | | | | | | | | | | | In type inference, an empty type set for a specific hw mode is not an error. In earlier stages of the design it was, but having to use non- parameterized types with target intrinsics necessarily led to type contradictions: since the intrinsics used specific types, they were only valid for a specific hw mode, and the resulting type set for other modes ended up empty. To accommodate the existence of such intrinsics individual type sets were allowed to be empty as long as not all sets were empty. llvm-svn: 315858
* revert r314984: revert r314698 - [InstCombine] remove one-use restriction ↵Sanjay Patel2017-10-152-7/+7
| | | | | | | | | for icmp (shr exact X, C1), C2 --> icmp X, (C2<<C1) Recommitting r314698. The bug exposed by this change should be fixed with: https://reviews.llvm.org/rL315579 llvm-svn: 315857
* [SimplifyCFG] use range-for-loops, tidy; NFCISanjay Patel2017-10-151-20/+10
| | | | | | | There seems to be something missing here as shown in PR34471: https://bugs.llvm.org/show_bug.cgi?id=34471 llvm-svn: 315855
* Reverting r315590; it did not include changes for llvm-tblgen, which is ↵Aaron Ballman2017-10-15113-173/+172
| | | | | | | | causing link errors for several people. Error LNK2019 unresolved external symbol "public: void __cdecl `anonymous namespace'::MatchableInfo::dump(void)const " (?dump@MatchableInfo@?A0xf4f1c304@@QEBAXXZ) referenced in function "public: void __cdecl `anonymous namespace'::AsmMatcherEmitter::run(class llvm::raw_ostream &)" (?run@AsmMatcherEmitter@?A0xf4f1c304@@QEAAXAEAVraw_ostream@llvm@@@Z) llvm-tblgen D:\llvm\2017\utils\TableGen\AsmMatcherEmitter.obj 1 llvm-svn: 315854
* [MergeFunctions] Merge small functions if possible without a thunk.whitequark2017-10-152-12/+24
| | | | | | | | | | This can result in significant code size savings in some cases, e.g. an interrupt table all filled with the same assembly stub in a certain Cortex-M BSP results in code blowup by a factor of 2.5. Differential Revision: https://reviews.llvm.org/D34806 llvm-svn: 315853
* [MergeFunctions] Replace all uses of unnamed_addr functions.whitequark2017-10-153-3/+57
| | | | | | | | | This reduces code size for constructs like vtables or interrupt tables that refer to functions in global initializers. Differential Revision: https://reviews.llvm.org/D34805 llvm-svn: 315852
* [X86] Ignore DBG instructions in X86CmovConversion optimization to resolve ↵Amjad Aboud2017-10-152-0/+91
| | | | | | | | PR34565 Differential Revision: https://reviews.llvm.org/D38359 llvm-svn: 315851
* [LoopInfo][Refactor] Make SetLoopAlreadyUnrolled a member function of the ↵Hongbin Zheng2017-10-154-67/+43
| | | | | | | | | | Loop Pass, NFC. This avoid code duplication and allow us to add the disable unroll metadata elsewhere. Differential Revision: https://reviews.llvm.org/D38928 llvm-svn: 315850
* [X86] Lower vselect with constant condition to vector_shuffle even with ↵Craig Topper2017-10-154-33/+14
| | | | | | | | | | | | | | | | | | | AVX512 instructions. Summary: It's better to use our shuffle lowering code to handle these than loading an immediate into a k-register. It really feels like this should be a DAG combine optimization rather than a lowering operation, but that's a problem for another day. Reviewers: RKSimon, delena, zvi Reviewed By: delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38932 llvm-svn: 315849
* [X86] Don't use constant condition for select instruction when testing ↵Craig Topper2017-10-1515-11688/+13891
| | | | | | | | masking ops. We should be able to fold constant conditions by converting to shuffles, but fixing that would break these tests in their current form. Since they are really trying to test masking ops, add a non-constant mask to the selects. llvm-svn: 315848
* Remove unused variablesVitaly Buka2017-10-156-7/+2
| | | | llvm-svn: 315847
* [globalisel][tablegen] Map ld and st to G_LOAD and G_STORE. NFCDaniel Sanders2017-10-154-10/+77
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: There is an important mismatch between ISD::LOAD and G_LOAD (and likewise for ISD::STORE and G_STORE). In SelectionDAG, ISD::LOAD is a non-atomic load and atomic loads are handled by a separate node. However, this is not true of GlobalISel's G_LOAD. For G_LOAD, the MachineMemOperand indicates the atomicity of the operation. As a result, this mapping must also add a predicate that checks for non-atomic MachineMemOperands. This is NFC since these nodes always have predicates in practice and are therefore always rejected at the moment. Depends on D37443 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37445 llvm-svn: 315843
* [tablegen] Handle common load/store predicates inside tablegen. NFC.Daniel Sanders2017-10-154-179/+533
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: GlobalISel and SelectionDAG require different code for the common load/store predicates due to differences in the representation. For example: SelectionDAG: (load<signext,i8>:i32 GPR32:$addr) // The <> denote properties of the SDNode that are not printed in the DAG GlobalISel: (G_SEXT:s32 (G_LOAD:s8 GPR32:$addr)) Even without that, differences in the IR (SDNode vs MachineInstr) require differences in the C++ predicate. This patch moves the implementation of the common load/store predicates into tablegen so that it can handle these differences. It's NFC for SelectionDAG since it emits equivalent code and it's NFC for GlobalISel since the rules involving the relevant predicates are still rejected by the importer. Depends on D36618 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37443 Includes a partial revert of r315826 since this patch makes it necessary for getPredCode() to return a std::string and getImmCode() should have the same interface as getPredCode(). llvm-svn: 315841
* [Hexagon] Mark RangeTree::dump() with LLVM_DUMP_METHOD.Davide Italiano2017-10-141-1/+1
| | | | | | | GCC otherwise emits a "defined but not used" warning on the member function. llvm-svn: 315838
* AMDGPU: Temporary disable pal metadata check line in llvm-readobj testKonstantin Zhuravlyov2017-10-141-1/+2
| | | | | | It fails on mips llvm-svn: 315837
* AMDGPU: Don't use TargetStreamer if it has not been initializedKonstantin Zhuravlyov2017-10-142-10/+16
| | | | | | | | | | Fixes cfe/trunk/test/Misc/backend-resource-limit-diagnostics.cl test after r315808 We may hit few other similar issues, but I want to discuss good solution offline. llvm-svn: 315830
* [X86] Remove a bunch of dead FileCheck lines with the wrong prefix.Craig Topper2017-10-141-1105/+0
| | | | llvm-svn: 315828
* [TableGen] Avoid unnecessary std::string creationsSimon Pilgrim2017-10-143-19/+18
| | | | | | Avoid unnecessary std::string creations in the TreePredicateFn getters. llvm-svn: 315826
* [X86][SSE] Don't attempt to reduce the imul vector width of odd sized ↵Simon Pilgrim2017-10-142-1/+109
| | | | | | vectors (PR34947) llvm-svn: 315825
* [X86][SSE] Test vector imul reduction on 32 and 64-bit targetsSimon Pilgrim2017-10-141-358/+846
| | | | llvm-svn: 315824
* Revert "[AArch64][RegisterBankInfo] Use the statically computed mappings for ↵Bruno Cardoso Lopes2017-10-141-32/+4
| | | | | | | | | COPY" This reverts commit r315781, breaks: http://green.lab.llvm.org/green/job/Compiler_Verifiers_GlobalISEL/9882 llvm-svn: 315823
* AMDGPU: Add AMDGPU HSA Kernel DescriptorKonstantin Zhuravlyov2017-10-142-91/+252
| | | | | | | | | | - Update docs to match llvm coding style - Add missing FP16_OVFL bit for gfx9 - Fix the size of the kernel descriptor in the docs Differential Revision: https://reviews.llvm.org/D38902 llvm-svn: 315822
* AMDGPU: Bring HSA metadata on par with the specificationKonstantin Zhuravlyov2017-10-1419-337/+428
| | | | | | Differential Revision: https://reviews.llvm.org/D38753 llvm-svn: 315821
* llvm-readobj: Print AMDGPU note contentsKonstantin Zhuravlyov2017-10-1412-68/+69
| | | | | | Differential Revision: https://reviews.llvm.org/D38752 llvm-svn: 315819
* Pull out repeated calls to VT.getVectorNumElements(). NFCI.Simon Pilgrim2017-10-141-10/+11
| | | | llvm-svn: 315818
* Cleanup update_llc_test_checks.py notes.Simon Pilgrim2017-10-145-5/+2
| | | | llvm-svn: 315817
* AMDGPU: Cleanup elf-notes.ll testKonstantin Zhuravlyov2017-10-141-26/+25
| | | | llvm-svn: 315816
* Use DAG::getBitcast() helper. NFCI.Simon Pilgrim2017-10-141-4/+4
| | | | llvm-svn: 315815
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