summaryrefslogtreecommitdiffstats
path: root/llvm
Commit message (Collapse)AuthorAgeFilesLines
* Documentation: AliasAnalysis.rst: improve internal and external linksDmitri Gribenko2012-12-121-19/+18
| | | | llvm-svn: 169993
* Documentation: convert WritingAnLLVMPass.html to reST.Dmitri Gribenko2012-12-128-1967/+1456
| | | | | | Patch by Anthony Mykhailenko with small fixes by me. llvm-svn: 169992
* Documentation: cleanupDmitri Gribenko2012-12-121-3/+4
| | | | llvm-svn: 169990
* The TargetData is not used for the isPowerOfTwo determination. It has neverRafael Espindola2012-12-124-18/+15
| | | | | | | | | | been used in the first place. It simply was passed to the function and to the recursive invocations. Simply drop the parameter and update the callers for the new signature. Patch by Saleem Abdulrasool! llvm-svn: 169988
* Improve debug info generated with enabled AddressSanitizer.Alexey Samsonov2012-12-125-0/+105
| | | | | | | | | | | | When ASan replaces <alloca instruction> with <offset into a common large alloca>, it should also patch llvm.dbg.declare calls and replace debug info descriptors to mark that we've replaced alloca with a value that stores an address of the user variable, not the user variable itself. See PR11818 for more context. llvm-svn: 169984
* Documentation: use a 'console' highlighter for terminal output examples. ThisDmitri Gribenko2012-12-122-11/+11
| | | | | | gives a nicer output than 'bash'. llvm-svn: 169981
* Documentation: use a 'console' highlighter for terminal output examples. ThisDmitri Gribenko2012-12-122-37/+37
| | | | | | gives a nicer output than 'bash'. llvm-svn: 169979
* llvm/test/CodeGen/X86/atom-bypass-slow-division.ll: Fix possible typo(s) in ↵NAKAMURA Takumi2012-12-121-4/+4
| | | | | | | | CHECK-NOT lines. Found by Alexander Zinenko, thanks! llvm-svn: 169978
* llvm/test/CodeGen/X86/atom-bypass-slow-division.ll: Rename symbols, ↵NAKAMURA Takumi2012-12-121-20/+20
| | | | | | s/test_/Test/g, not to mismatch "CHECK(-NOT): test". llvm-svn: 169977
* Add ARM NONE and PREL31 relocation types.Logan Chien2012-12-123-3/+16
| | | | | | | | Add R_ARM_NONE and R_ARM_PREL31 relocation types to MCExpr. Both of them will be used while generating .ARM.extab and .ARM.exidx sections. llvm-svn: 169965
* Remove some dead code.Rafael Espindola2012-12-121-8/+0
| | | | llvm-svn: 169963
* [CMake] Fixup R600.NAKAMURA Takumi2012-12-121-1/+1
| | | | llvm-svn: 169962
* Sorry about the churn. One more change to getOptimalMemOpType() hook. Did IEvan Cheng2012-12-1210-44/+43
| | | | | | | | | | | | mention the inline memcpy / memset expansion code is a mess? This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset. The first indicates whether it is expanding a memset or a memcpy / memmove. The later is whether the memset is a memset of zero. It's totally possible (likely even) that targets may want to do different things for memcpy and memset of zero. llvm-svn: 169959
* llvm/test/CodeGen/X86/store_op_load_fold.ll: Fix typo, s/CHECK_NEXT/CHECK-NEXT/NAKAMURA Takumi2012-12-121-1/+1
| | | | llvm-svn: 169957
* llvm/test/CodeGen/X86/store_op_load_fold.ll: Add explicit triple.NAKAMURA Takumi2012-12-121-1/+1
| | | | llvm-svn: 169956
* Fix the ascii drawing that was ruined when I split the H and CPPNadav Rotem2012-12-121-10/+10
| | | | llvm-svn: 169955
* - Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.Evan Cheng2012-12-1210-43/+34
| | | | | | | | | Also added more comments to explain why it is generally ok to return true. - Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to be true for loaded source (memcpy) or zero constants (memset). The poor name choice is probably some kind of legacy issue. llvm-svn: 169954
* fix a typo.Nadav Rotem2012-12-121-1/+1
| | | | llvm-svn: 169953
* DAGCombine: clamp hi bit in APInt::getBitsSet to avoid assertionManman Ren2012-12-122-2/+20
| | | | | | rdar://12838504 llvm-svn: 169951
* LoopVectorizer: When -Os is used, vectorize only loops that dont require a ↵Nadav Rotem2012-12-126-31/+70
| | | | | | tail loop. There is no testcase because I dont know of a way to initialize the loop vectorizer pass without adding an additional hidden flag. llvm-svn: 169950
* Avoid using lossy load / stores for memcpy / memset expansion. e.g.Evan Cheng2012-12-127-17/+58
| | | | | | f64 load / store on non-SSE2 x86 targets. llvm-svn: 169944
* Have SimplifyBinOp call the new FAdd/FSub/FMul helpers, with fast-math flags offMichael Ilseman2012-12-121-0/+8
| | | | llvm-svn: 169943
* - Fix a problematic way in creating all-the-1 APInt.Shuxin Yang2012-12-122-2/+14
| | | | | | - Propagate "exact" bit of [l|a]shr instruction. llvm-svn: 169942
* Remove redunant optimizations from InstCombine, instead call the appropriate ↵Michael Ilseman2012-12-122-30/+9
| | | | | | functions from SimplifyInstruction llvm-svn: 169941
* Added a slew of SimplifyInstruction floating-point optimizations, many of ↵Michael Ilseman2012-12-124-10/+230
| | | | | | | | | | | | | | | | which take advantage of fast-math flags. Test cases included. fsub X, +0 ==> X fsub X, -0 ==> X, when we know X is not -0 fsub +/-0.0, (fsub -0.0, X) ==> X fsub nsz +/-0.0, (fsub +/-0.0, X) ==> X fsub nnan ninf X, X ==> 0.0 fadd nsz X, 0 ==> X fadd [nnan ninf] X, (fsub [nnan ninf] 0, X) ==> 0 where nnan and ninf have to occur at least once somewhere in this expression fmul X, 1.0 ==> X llvm-svn: 169940
* Pattern matchers for floating point valuesMichael Ilseman2012-12-121-0/+56
| | | | | | | | | | m_ConstantFP - match and bind a float constant m_SpecificConstantFP - match a specific floating point value or vector of floats of that value m_FPOne - match a floating point 1.0 or vector of 1.0s m_NegZero - match -0.0 m_AnyZero - match 0 or -0.0 llvm-svn: 169939
* Remove FIXMEs surrounding Constant[Data]Vectors, insteadMichael Ilseman2012-12-121-35/+19
| | | | llvm-svn: 169938
* Trim unneeded header #include.Jim Grosbach2012-12-111-1/+0
| | | | llvm-svn: 169933
* Documentation: cleanup: remove useless anchors and write :ref:s explicitly.Dmitri Gribenko2012-12-111-27/+8
| | | | llvm-svn: 169932
* ARM: Remove old testing option.Jim Grosbach2012-12-111-5/+1
| | | | | | | Pre-regalloc frame allocation and referencing has been on by default for ages. No need for the testing option that disables it. llvm-svn: 169931
* ARM: Remove old testing options.Jim Grosbach2012-12-111-13/+0
| | | | | | Base pointer referencing has been enabled for ages. llvm-svn: 169930
* Replace TargetLowering::isIntImmLegal() withEvan Cheng2012-12-116-33/+58
| | | | | | | | | ScalarTargetTransformInfo::getIntImmCost() instead. "Legal" is a poorly defined term for something like integer immediate materialization. It is always possible to materialize an integer immediate. Whether to use it for memcpy expansion is more a "cost" conceern. llvm-svn: 169929
* Documentation: Lexicon.rst: add 'SLP' acronymDmitri Gribenko2012-12-111-1/+7
| | | | llvm-svn: 169928
* PR14574. Fix a bug in the code that calculates the mask the converted PHIs ↵Nadav Rotem2012-12-112-1/+45
| | | | | | in if-conversion. llvm-svn: 169916
* Add R600 backendTom Stellard2012-12-11146-1/+20232
| | | | | | A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
* This patch implements the general dynamic TLS model for 64-bit PowerPC.Bill Schmidt2012-12-1115-15/+246
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Given a thread-local symbol x with global-dynamic access, the generated code to obtain x's address is: Instruction Relocation Symbol addis ra,r2,x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x addi r3,ra,x@got@tlsgd@l R_PPC64_GOT_TLSGD16_L x bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x R_PPC64_REL24 __tls_get_addr nop <use address in r3> The implementation borrows from the medium code model work for introducing special forms of ADDIS and ADDI into the DAG representation. This is made slightly more complicated by having to introduce a call to the external function __tls_get_addr. Using the full call machinery is overkill and, more importantly, makes it difficult to add a special relocation. So I've introduced another opcode GET_TLS_ADDR to represent the function call, and surrounded it with register copies to set up the parameter and return value. Most of the code is pretty straightforward. I ran into one peculiarity when I introduced a new PPC opcode BL8_NOP_ELF_TLSGD, which is just like BL8_NOP_ELF except that it takes another parameter to represent the symbol ("x" above) that requires a relocation on the call. Something in the TblGen machinery causes BL8_NOP_ELF and BL8_NOP_ELF_TLSGD to be treated identically during the emit phase, so this second operand was never visited to generate relocations. This is the reason for the slightly messy workaround in PPCMCCodeEmitter.cpp:getDirectBrEncoding(). Two new tests are included to demonstrate correct external assembly and correct generation of relocations using the integrated assembler. Comments welcome! Thanks, Bill llvm-svn: 169910
* Update some comments.Eric Christopher2012-12-112-6/+6
| | | | llvm-svn: 169907
* Loop Vectorize: optimize the vectorization of trunc(induction_var). The ↵Nadav Rotem2012-12-115-5/+46
| | | | | | truncation is now done on scalars. llvm-svn: 169904
* Remove the RelaxAll overrule in MCAssembler::fixupNeedsRelaxation,Eli Bendersky2012-12-111-3/+2
| | | | | | | | | | | | because that method is only getting called for MCInstFragment. These fragments aren't even generated when RelaxAll is set, which is why the flag reference here is superfluous. Removing it simplifies the code with no harmful effects. An assertion is added higher up to make sure this path is never reached. llvm-svn: 169886
* Use an ArrayRef instead of a std::vector&.Rafael Espindola2012-12-112-6/+6
| | | | llvm-svn: 169881
* Add comment for load foldingJoel Jones2012-12-111-0/+5
| | | | llvm-svn: 169880
* Documentation: convert Passes.html to reST.Dmitri Gribenko2012-12-112-2025/+1264
| | | | | | | | | Since now we have an autogenerated TOC, a manually written table of all passes was removed. Patch by Anthony Mykhailenko with small fixes by me. llvm-svn: 169867
* llvm/test/TableGen: Remove XFAIL:vg_leak in dozen of tests, according to ↵NAKAMURA Takumi2012-12-1136-36/+0
| | | | | | llvm-x86_64-linux-vg_leak. llvm-svn: 169862
* [msan] Use explicitely aligned stores and loads with function argument shadow.Evgeniy Stepanov2012-12-111-8/+13
| | | | | | | | Use explicitely aligned store and load instructions to deal with argument and retval shadow. This matters when an argument's alignment is higher than __msan_param_tls alignment (which is the case with __m128i). llvm-svn: 169859
* Revert EVT->MVT changes, r169836-169851, due to buildbot failures.Patrik Hagglund2012-12-1128-281/+245
| | | | llvm-svn: 169854
* Holding my nose and moving the accumulation routine to GEPOperatorChandler Carruth2012-12-113-62/+44
| | | | | | | | | | | | | | | | | instead of the instruction. I've left a forwarding wrapper for the instruction so users with the instruction don't need to create a GEPOperator themselves. This lets us remove the copy of this code in instsimplify. I've looked at most of the other copies of similar code, and this is the only one I've found that is actually exactly the same. The one in InlineCost is very close, but it requires re-mapping non-constant indices through the cost analysis value simplification map. I could add direct support for this to the generic routine, but it seems overly specific. llvm-svn: 169853
* Hoist the GEP constant address offset computation to a common home onChandler Carruth2012-12-114-25/+46
| | | | | | | | | | | the GEP instruction class. This is part of the continued refactoring and cleaning of the infrastructure used by SROA. This particular operation is also done in a few other places which I'll try to refactor to share this implementation. llvm-svn: 169852
* Change RegVT in BitTestBlock and RegsForValue, to contain MVTs,Patrik Hagglund2012-12-112-13/+12
| | | | | | instead of EVTs. llvm-svn: 169851
* Change TargetLowering::getTypeForExtArgOrReturn to take and returnPatrik Hagglund2012-12-115-8/+30
| | | | | | | | MVTs, instead of EVTs. Accordingly, add bitsLT (and similar) to MVT. llvm-svn: 169850
* Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT,Patrik Hagglund2012-12-113-18/+25
| | | | | | from EVT. llvm-svn: 169849
OpenPOWER on IntegriCloud