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* [X86] Remove MVT::i1 handling code from LowerTRUNCATECraig Topper2017-10-111-8/+0
| | | | | | | | | | | | | | Summary: I don't think this is necessary with i1 being illegal now. Reviewers: RKSimon, zvi, guyblank Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38784 llvm-svn: 315469
* [Pipeliner] Fix offset value for instrs dependent on post-inc load/storesKrzysztof Parzyszek2017-10-112-10/+16
| | | | | | | | | | | | The software pipeliner and the packetizer try to break dependence between the post-increment instruction and the dependent memory instructions by changing the base register and the offset value. However, in some cases, the existing logic didn't work properly and created incorrect offset value. Patch by Jyotsna Verma. llvm-svn: 315468
* [Pipeliner] Improve serialization order for post-incrementsKrzysztof Parzyszek2017-10-115-14/+157
| | | | | | | | | | | | | | | | | | | The pipeliner is generating a serial sequence that causes poor register allocation when a post-increment instruction appears prior to the use of the post-increment register. This occurs when there is a circular set of dependences involved with a sequence of instructions in the same cycle. In this case, there is no serialization of the parallel semantics that will not cause an additional register to be allocated. This patch fixes the problem by changing the instructions so that the post-increment instruction is used by the subsequent instruction, which enables the register allocator to make a better decision and not require another register. Patch by Brendon Cahoon. llvm-svn: 315466
* [InstCombine] add baseline tests for D38531; NFCSanjay Patel2017-10-111-1/+103
| | | | llvm-svn: 315461
* [DAGCombiner] convert insertelement of bitcasted vector into shuffleSanjay Patel2017-10-113-51/+77
| | | | | | | | | | | | | | | | Eg: insert v4i32 V, (v2i16 X), 2 --> shuffle v8i16 V', X', {0,1,2,3,8,9,6,7} This is a generalization of the IR fold in D38316 to handle insertion into a non-undef vector. We may want to abandon that one if we can't find value in squashing the more specific pattern sooner. We're using the existing legal shuffle target hook to avoid AVX512 horror with vXi1 shuffles. There may be room for improvement in the shuffle lowering here, but that would be follow-up work. Differential Revision: https://reviews.llvm.org/D38388 llvm-svn: 315460
* Revert "[dsymutil] Timestmap verification for __swift_ast"Jonas Devlieghere2017-10-117-74/+23
| | | | | | This reverts commit r315456. llvm-svn: 315458
* [TargetLowering] Correctly track NumFixedArgs field of CallLoweringInfoAlex Bradbury2017-10-112-2/+3
| | | | | | | | | | | | | | | | | | | | | The NumFixedArgs field of CallLoweringInfo is used by TargetLowering::LowerCallTo to determine whether a given argument is passed using the vararg calling convention or not (specifically, to set IsFixed for each ISD::OutputArg). Firstly, CallLoweringInfo::setLibCallee and CallLoweringInfo::setCallee both incorrectly set NumFixedArgs based on the _previous_ args list. Secondly, TargetLowering::LowerCallTo failed to increment NumFixedArgs when modifying the argument list so a pointer is passed for the return value. If your backend uses the IsFixed property or directly accesses NumFixedArgs, it is _possible_ this change could result in codegen changes (although the previous behaviour would have been incorrect). No such cases have been identified during code review for any in-tree architecture. Differential Revision: https://reviews.llvm.org/D37898 llvm-svn: 315457
* [dsymutil] Timestmap verification for __swift_astJonas Devlieghere2017-10-117-23/+74
| | | | | | | | | | | | This patch adds timestamp verification for swiftmodule files. - A new flag is provided to allows us to continue testing of the code for embedding the__swift_ast. (git doesn't maintain timestamps) - Adds a new test for fat (arm) binaries. Differential revision: https://reviews.llvm.org/D38686 llvm-svn: 315456
* [RISCV] Fix build after r315327Alex Bradbury2017-10-113-6/+10
| | | | | | | Differential Revision: https://reviews.llvm.org/D38779 Patch by Chih-Mao Chen. llvm-svn: 315455
* [mips] Add missing tests from rL315451Simon Dardis2017-10-114-0/+704
| | | | llvm-svn: 315454
* [mips] Add support for parsing target specific flags for MIRSimon Dardis2017-10-112-0/+42
| | | | | | | | Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D38620 llvm-svn: 315451
* llvm/module.modulemap: Create LLVM_MC_TableGen. It is used by llvm-tblgen.NAKAMURA Takumi2017-10-111-0/+10
| | | | llvm-svn: 315450
* llvm/module.modulemap: Move Support_TargetRegistry to let LLVMSupport free ↵NAKAMURA Takumi2017-10-111-6/+7
| | | | | | from MC. llvm-svn: 315449
* [NFC] Fix variables used only for assert in GVNMax Kazantsev2017-10-111-6/+6
| | | | llvm-svn: 315448
* [llvm-rc] Fix spelling in messageSimon Dardis2017-10-111-1/+1
| | | | llvm-svn: 315447
* [TableGen] Tidy up CodeGenSchedule.cppJaved Absar2017-10-111-13/+13
| | | | | | Use range_loop where it simplifies. llvm-svn: 315446
* [Asm] Add debug tracing in table-generated assembly matcherOliver Stannard2017-10-1116-30/+122
| | | | | | | | | | | | | This adds debug tracing to the table-generated assembly instruction matcher, enabled by the -debug-only=asm-matcher option. The changes in the target AsmParsers are to add an MCInstrInfo reference under a consistent name, so that we can use it from table-generated code. This was already being used this way for targets that use deprecation warnings, but 5 targets did not have it, and Hexagon had it under a different name to the other backends. llvm-svn: 315445
* [X86] Added tests for TESTM and TESTNM (NFC)Uriel Korach2017-10-114-0/+1148
| | | | | | | | Adding this test files now so after another commit that will add a new pattern for TESTM and TESTNM instructions will show the improvemnts that have been done. Change-Id: If3908b7f91897d764053312365a2bc1de78b291d llvm-svn: 315443
* [GVN] Prevent LoadPRE from hoisting across instructions that don't pass ↵Max Kazantsev2017-10-114-0/+258
| | | | | | | | | | | | | | | | | | control flow to successors This patch fixes the miscompile that happens when PRE hoists loads across guards and other instructions that don't always pass control flow to their successors. PRE is now prohibited to hoist across such instructions because there is no guarantee that the load standing after such instruction is still valid before such instruction. For example, a load from under a guard may be invalid before the guard in the following case: int array[LEN]; ... guard(0 <= index && index < LEN); use(array[index]); Differential Revision: https://reviews.llvm.org/D37460 llvm-svn: 315440
* [LICM] Disallow sinking of unordered atomic loads into loopsMax Kazantsev2017-10-112-5/+104
| | | | | | | | | | | | | | | | | | | | | | | | Sinking of unordered atomic load into loop must be disallowed because it turns a single load into multiple loads. The relevant section of the documentation is: http://llvm.org/docs/Atomics.html#unordered, specifically the Notes for Optimizers section. Here is the full text of this section: > Notes for optimizers > In terms of the optimizer, this **prohibits any transformation that > transforms a single load into multiple loads**, transforms a store into > multiple stores, narrows a store, or stores a value which would not be > stored otherwise. Some examples of unsafe optimizations are narrowing > an assignment into a bitfield, rematerializing a load, and turning loads > and stores into a memcpy call. Reordering unordered operations is safe, > though, and optimizers should take advantage of that because unordered > operations are common in languages that need them. Patch by Daniil Suchkov! Reviewed By: reames Differential Revision: https://reviews.llvm.org/D38392 llvm-svn: 315438
* [IRCE] Do not process empty safe rangesMax Kazantsev2017-10-113-9/+85
| | | | | | | | | | | | | | | IRCE should not apply when the safe iteration range is proved to be empty. In this case we do unneeded job creating pre/post loops and then never go to the main loop. This patch makes IRCE not apply to empty safe ranges, adds test for this situation and also modifies one of existing tests where it used to happen slightly. Reviewed By: anna Differential Revision: https://reviews.llvm.org/D38577 llvm-svn: 315437
* [GVN] Don't replace constants with constants.Davide Italiano2017-10-112-0/+18
| | | | | | | | This fixes PR34908. Patch by Alex Crichton! Differential Revision: https://reviews.llvm.org/D38765 llvm-svn: 315429
* Revert "[llvm-objcopy] Add support for --strip-sections to remove all ↵Jake Ehrlich2017-10-114-114/+20
| | | | | | | | section headers leaving only program headers and loadable segment data" This reverts commit rL315412 llvm-svn: 315417
* WIN32_FIND_DATA -> WIN32_FIND_DATAW.Peter Collingbourne2017-10-111-1/+1
| | | | | | Should fix mingw bot. llvm-svn: 315413
* [llvm-objcopy] Add support for --strip-sections to remove all section ↵Jake Ehrlich2017-10-114-20/+114
| | | | | | | | | | | | | | | | | | headers leaving only program headers and loadable segment data elf utils implements a particularly extreme form of stripping that I'd like to support. eu-strip has an option called "strip-sections" that removes all section headers and leaves only program headers and the segment data. I have implemented this option partly as a test but mainly because in Fuchsia we would like to use this option to minimize the size of our executables. The other strip options that are on my list include --strip-all and --strip-debug. This is a preliminary implementation that I'd like to start using in Fuchsia builds if possible. This change implements such a stripping option for llvm-objcopy Differential Revision: https://reviews.llvm.org/D38335 llvm-svn: 315412
* [MC] Have MCObjectStreamer take its MCAsmBackend argument via unique_ptr.Lang Hames2017-10-1139-185/+252
| | | | | | | | MCObjectStreamer owns its MCAsmBackend -- this fixes the types to reflect that, and allows us to remove another instance of MCObjectStreamer's weird "holding ownership via someone else's reference" trick. llvm-svn: 315410
* Silence MSVC warnings about unsigned wrapping without UBReid Kleckner2017-10-111-7/+5
| | | | | | | | | | | Of course, casting an unsigned value too large for 'int' is UB. So, write out the ternary. LLVM folds it to ADD anyway. Fixes the warning from r303693 a different way. Thanks to Erich Keane for pointing this out! llvm-svn: 315406
* [X86] Remove temporary std::string creation from shuffle comment printing. ↵Craig Topper2017-10-111-12/+12
| | | | | | We can just write directly to the raw_ostream. llvm-svn: 315399
* [X86] Add 128-bit version of vbroadcasti32x2 to shuffle comment decoding.Craig Topper2017-10-113-10/+21
| | | | llvm-svn: 315395
* CodeGen: Minor cleanups to use MachineInstr::getMF. NFCJustin Bogner2017-10-1020-50/+45
| | | | | | | Since r315388 we have a shorter way to say this, so we'll replace MI->getParent()->getParent() with MI->getMF() in a few places. llvm-svn: 315390
* CodeGen: Add MachineInstr::getMF(). NFCJustin Bogner2017-10-102-0/+15
| | | | | | | | Similarly to how Instruction has getFunction, this adds a less verbose way to write MI->getParent()->getParent(). I'll follow up shortly with a change that changes a bunch of the uses. llvm-svn: 315388
* [llvm-objcopy] Add ability to remove multiple sections by nameJake Ehrlich2017-10-102-6/+139
| | | | | | | | | This change adds the ability to use the "-R"/"-remove-section" option multiple times. Differential Revision: https://reviews.llvm.org/D38332 llvm-svn: 315385
* [Transforms] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-10-1014-157/+316
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 315383
* [X86] Add broadcast patterns that allow a scalar_to_vector between the ↵Craig Topper2017-10-102-2/+19
| | | | | | | | broadcast and the load. We already have these patterns for AVX512VL, but not AVX1 or 2. llvm-svn: 315382
* [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-10-1018-214/+414
| | | | | | other minor fixes (NFC). llvm-svn: 315380
* Support: Have directory_iterator::status() return ↵Peter Collingbourne2017-10-106-113/+154
| | | | | | | | | | | | | | | | | | FindFirstFileEx/FindNextFile results on Windows. This allows clients to avoid an unnecessary fs::status() call on each directory entry. Because the information returned by FindFirstFileEx is a subset of the information returned by a regular status() call, I needed to extract a base class from file_status that contains only that information. On my machine, this reduces the time required to enumerate a ThinLTO cache directory containing 520k files from almost 4 minutes to less than 2 seconds. Differential Revision: https://reviews.llvm.org/D38716 llvm-svn: 315378
* Make the ELFFile constructor private.Rafael Espindola2017-10-104-12/+27
| | | | | | | | | With this all clients have to use the new create method which returns an Expected. Fixes a crash on invalid input. llvm-svn: 315376
* [SparsePropagation] Let the Instruction work list hold Values.Matthew Simpson2017-10-101-15/+14
| | | | llvm-svn: 315375
* [SparsePropagation] Use SmallVector for work listsMatthew Simpson2017-10-101-6/+12
| | | | | | | This patch changes the work lists from std::vector to SmallVector, which matches the SCCP implementation. This patch also updates some related comments. llvm-svn: 315373
* [llvm-objcopy] Fix latent bug that allowed some Sections to be improperly ↵Jake Ehrlich2017-10-102-18/+21
| | | | | | | | | | | | | | | | cast to StringTableSections If a Section had Type SHT_STRTAB (which could happen if you had a .dynstr section) it was possible to cast Section to StringTableSection and get away with any operation that was supported by SectionBase without it being noticed. This change makes this bug easier to notice and fixes it where it occurred. It also made me realize that there was some duplication of efforts in the loop that calls ::initialize. These issues are all fixed by this change. Differential Revision: https://reviews.llvm.org/D38329 llvm-svn: 315372
* Make the ELFObjectFile constructor private.Rafael Espindola2017-10-104-48/+80
| | | | | | | This forces every user to use the new create method that returns an Expected. This in turn propagates better error messages. llvm-svn: 315371
* Revert "Classify llvm-cfi-verify."Vlad Tsyrklevich2017-10-107-682/+196
| | | | | | | | This reverts commit r315363. It has a simple build failure, but more importantly I want to confirm that unit tests run in check-all to make sure that they don't silently break in the future. llvm-svn: 315370
* Use the first instruction's count to estimate the funciton's entry frequency.Dehao Chen2017-10-103-12/+48
| | | | | | | | | | | | | | Summary: In the current implementation, we only have accurate profile count for standalone symbols. For inlined functions, we do not have entry count data because it's not available in LBR. In this patch, we use the first instruction's frequency to estimiate the function's entry count, especially for inlined functions. This may be inaccurate due to debug info in optimized code. However, this is a better estimate than the static 80/20 estimation we have in the current implementation. Reviewers: tejohnson, davidxl Reviewed By: tejohnson Subscribers: sanjoy, llvm-commits, aprantl Differential Revision: https://reviews.llvm.org/D38478 llvm-svn: 315369
* [x86] fix prefix typos for CHECK lines; NFCSanjay Patel2017-10-101-586/+290
| | | | llvm-svn: 315368
* [X86] Fix some patterns that select VLX instructions, but were incorrectly ↵Craig Topper2017-10-102-2/+6
| | | | | | | | also checking presence of BWI instructions. The EVEX->VEX pass probably obscures this. llvm-svn: 315365
* Simplify. NFC.Rafael Espindola2017-10-101-4/+4
| | | | llvm-svn: 315364
* Classify llvm-cfi-verify.Vlad Tsyrklevich2017-10-107-196/+682
| | | | | | | | | | | | | | Summary: Move llvm-cfi-verify into a class in preparation for CFI analysis to come. Reviewers: vlad.tsyrklevich Reviewed By: vlad.tsyrklevich Subscribers: mgorny, llvm-commits, pcc, kcc Differential Revision: https://reviews.llvm.org/D38379 llvm-svn: 315363
* [mips] Correct the instruction predicates for microMIPSr3Simon Dardis2017-10-102-206/+226
| | | | | | | | | | | | | | | | Rather than using the AdditionalPredicates mechanism to guard the microMIPS instructions, use the existing predicates to properly guard those instructions. This also resolves a case where an instruction pattern was incorrectly available for microMIPS32R6, which caused a register allocation failure as the registers specified in the pattern were not available. Reviewers: nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D38451 llvm-svn: 315362
* AMDGPU: Fix missing skipFunction callsMatt Arsenault2017-10-103-2/+5
| | | | llvm-svn: 315361
* AMDGPU: Fix failure to select branch with optnoneMatt Arsenault2017-10-104-20/+60
| | | | | | | | opt-bisect/optnone disable the AMDGPUUniformAnnotateValues pass. The heuristic in the custom selector for brcond deferred the branch uniformity check to the pattern, which would fail. llvm-svn: 315360
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