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* Fix sign compare warning in unit test by using an explicit unsigned literal ↵David Blaikie2017-03-131-1/+1
| | | | | | suffix llvm-svn: 297674
* [IPRA] Change algorithm for RegUsageInfoCollector.Marcello Maggioni2017-03-131-3/+21
| | | | | | | | | | | | | | | | | The previous algorithm for RegUsageInfoCollector had pretty bad performance on architectures with a lot of registers that alias a lot one another, because we potentially iterate for every register over all the aliasing registers. This costs even more if the function is small and doesn't define a lot of registers. This patch changes the algorithm to one that while iterating over all the registers it will iterate over the aliasing registers only if the register itself is defined. This should be faster based on the assumption that only a subset of the whole LLVM registers set is actually defined in the function. Differential Revision: https://reviews.llvm.org/D30880 llvm-svn: 297673
* [Support] Follow-up for "Test directory iterators and recursive directory ↵Juergen Ributzka2017-03-131-1/+1
| | | | | | | | iterators with broken symlinks." Fix the test by sorting the result vector. llvm-svn: 297672
* GlobalISel: Translate ConstantDataVectorVolkan Keles2017-03-132-0/+47
| | | | | | | | | | | | Reviewers: qcolombet, aditya_nandakumar, dsanders, t.p.northover, javed.absar, ab Reviewed By: qcolombet, dsanders, ab Subscribers: dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30216 llvm-svn: 297670
* [Support] Test directory iterators and recursive directory iterators with ↵Juergen Ributzka2017-03-131-0/+78
| | | | | | | | | | | broken symlinks. This commit adds a unit test to the file system tests to verify the behavior of the directory iterator and recursive directory iterator with broken symlinks. This test is Unix only. llvm-svn: 297669
* Revert "GlobalISel: move vector extract/insert inside generic opcode region."Tim Northover2017-03-132-14/+3
| | | | | | I was writing against an earlier branch and Volkan had already fixed this. llvm-svn: 297668
* [X86][MMX] Fix folding of shift value loads to cover whole 64-bitsSimon Pilgrim2017-03-134-54/+53
| | | | | | | | | | | | rL230225 made the assumption that only the lower 32-bits of an MMX register load is used as a shift value, when in fact the whole 64-bits are reloaded and treated as a i64 to determine the shift value. This patch reverts rL230225 to ensure that the whole 64-bits of memory are folded and ensures that the upper 32-bit are zero'd for cases where the shift value has come from a scalar source. Found during fuzz testing. Differential Revision: https://reviews.llvm.org/D30833 llvm-svn: 297667
* GlobalISel: move vector extract/insert inside generic opcode region.Tim Northover2017-03-132-3/+14
| | | | | | | Otherwise they won't be legalized or selected, causing instruction selection to fail horribly. llvm-svn: 297666
* Revert r295004 (Add MXCSR) due to errors reported by MachineVerifierAndrew Kaylor2017-03-134-38/+25
| | | | | | I am leaving the code in clang which filters mxcsr from the clobber list because that is still technically correct and will be useful again when the MXCSR register is reintroduced. llvm-svn: 297664
* [GlobalISel] Update PRE_ISEL_GENERIC_OPCODE_END markerVolkan Keles2017-03-131-1/+1
| | | | llvm-svn: 297663
* AMDGPU: Re-use TM.getNullPointerValueMatt Arsenault2017-03-131-10/+8
| | | | llvm-svn: 297662
* Bring back r297624.Rafael Espindola2017-03-133-1/+25
| | | | | | The issues was just a missing REQUIRES in the test. llvm-svn: 297661
* [SimplifyCFG] move tests for PR31028 from CGPSanjay Patel2017-03-131-8/+5
| | | | | | Hopefully, this will make sense with a forthcoming patch. If not, we can move these back. llvm-svn: 297660
* AMDGPU: Treat 0 as private null pointer in addrspacecast loweringMatt Arsenault2017-03-134-17/+23
| | | | llvm-svn: 297658
* Revert "Fix crash when multiple raw_fd_ostreams to stdout are created."Rafael Espindola2017-03-133-23/+1
| | | | | | | This reverts commit r297624. It was failing on the bots. llvm-svn: 297657
* Fix some indenting and line-wrapping issues identified in ProgrammersManual. ↵Daniel Berlin2017-03-131-26/+28
| | | | | | Make description of debugCounters a little clearer llvm-svn: 297656
* [Outliner] Add tail call supportJessica Paquette2017-03-136-48/+159
| | | | | | | | | | | | | | This commit adds tail call support to the MachineOutliner pass. This allows the outliner to insert jumps rather than calls in areas where tail calling is possible. Outlined tail calls include the return or terminator of the basic block being outlined from. Tail call support allows the outliner to take returns and terminators into consideration while finding candidates to outline. It also allows the outliner to save more instructions. For example, in the X86-64 outliner, a tail called outlined function saves one instruction since no return has to be inserted. llvm-svn: 297653
* [X86] Lower AVX2 gather intrinsics similar to AVX-512. Apply the same input ↵Craig Topper2017-03-135-86/+86
| | | | | | | | source optimizations to break execution dependencies. For AVX-512 we force the input to zero if the input is undef or the mask is all ones to break an execution dependency. This patch brings the same behavior to AVX2. llvm-svn: 297652
* [AVX-512] If gather mask is all ones, force the input to a zero vector.Craig Topper2017-03-132-40/+44
| | | | | | | | We were already forcing undef inputs to become a zero vector, this now catches an all ones mask too. Ideally we'd use undef and let execution dep fix handle picking the best register/clearance for the undef, but I don't think it can handle the early clobber today. llvm-svn: 297651
* AMDGPU: Fold icmp/fcmp into icmp intrinsicMatt Arsenault2017-03-132-0/+398
| | | | | | | The typical use is a library vote function which compares to 0. Fold the user condition into the intrinsic. llvm-svn: 297650
* [Linker] Provide callback for internalizationJonas Devlieghere2017-03-135-25/+69
| | | | | | Differential Revision: https://reviews.llvm.org/D30738 llvm-svn: 297649
* [SelectionDAG] Enhance SDTCisSameNumEltsAs to work with scalar types and use ↵Craig Topper2017-03-133-45/+64
| | | | | | | | | | | | it on extend/trunc/round operations. Currently we don't enforce that ISD::ANY_EXTEND, ZERO_EXTEND, SIGN_EXTEND, TRUNC, FP_ROUND, FP_EXTEND have the same number of elements(including scalar) between their input and output. Though we have them documented as such. Up until a few months ago x86 created nodes that violated this rule. That's all been fixed now, and we should enforce the rule going forward. In order to do this we need to allow SDTCisSameNumEltsAs to support scalar types and not enforce being a vector. If one type is scalar we will force the other type to also be scalar. Differential Revision: https://reviews.llvm.org/D30878 llvm-svn: 297648
* Add missing include on <limits>.Zachary Turner2017-03-131-0/+1
| | | | llvm-svn: 297646
* API gardening: Rename FindAllocaDbgValue to findDbgValue (NFC)Adrian Prantl2017-03-132-12/+8
| | | | | | | | and use have it use SmallVectorImpl. There is nothing specific about allocas in this function. llvm-svn: 297643
* Use numeric_limits<size_t>::max() instead of size_t(-1).Zachary Turner2017-03-131-2/+5
| | | | llvm-svn: 297641
* Fix a warning due to signed/unsigned comparison.Zachary Turner2017-03-131-1/+1
| | | | llvm-svn: 297639
* Use the new member accessors of llvm::enumerate.Zachary Turner2017-03-131-3/+3
| | | | | | | The value_type is no longer a struct, it's a class whose members you have to access via a method. llvm-svn: 297635
* [ADT] Improve the genericity of llvm::enumerate().Zachary Turner2017-03-133-40/+98
| | | | | | | | | | | | | | There were some issues in the implementation of enumerate() preventing it from being used in various contexts. These were all related to the fact that it did not supporter llvm's iterator_facade_base class. So this patch adds support for that and additionally exposes a new helper method to_vector() that will evaluate an entire range and store the results in a vector. Differential Revision: https://reviews.llvm.org/D30853 llvm-svn: 297633
* Remove an unused variable.Zachary Turner2017-03-131-1/+0
| | | | llvm-svn: 297632
* [CGP] add tests for PR31028; NFCSanjay Patel2017-03-131-0/+122
| | | | llvm-svn: 297629
* [llvm-pdbdump] Add support for dumping symbols from Yaml -> PDB.Zachary Turner2017-03-136-65/+98
| | | | | | | | Previously we could round-trip type records from PDB -> Yaml -> PDB, but for symbols we could only go from PDB -> Yaml. This completes the round-tripping for symbols as well. llvm-svn: 297625
* Fix crash when multiple raw_fd_ostreams to stdout are created.Rafael Espindola2017-03-133-1/+23
| | | | | | | | | | | | | | | | | | | | | If raw_fd_ostream is constructed with the path of "-", it claims ownership of the stdout file descriptor. This means that it closes stdout when it is destroyed. If there are multiple users of raw_fd_ostream wrapped around stdout, then a crash can occur because of operations on a closed stream. An example of this would be running something like "clang -S -o - -MD -MF - test.cpp". Alternatively, using outs() (which creates a local version of raw_fd_stream to stdout) anywhere combined with such a stream usage would cause the crash. The fix duplicates the stdout file descriptor when used within raw_fd_ostream, so that only that particular descriptor is closed when the stream is destroyed. Patch by James Henderson! llvm-svn: 297624
* [ARM] GlobalISel: Support SP in regbankselectDiana Picus2017-03-132-0/+36
| | | | | | | We used to hit an unreachable in getRegBankFromRegClass when dealing with the stack pointer. This commit adds support for the GPRsp reg class. llvm-svn: 297621
* Reverting r297617 because it broke some bots:Aaron Ballman2017-03-135-304/+55
| | | | | | http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/49970 llvm-svn: 297618
* Add support for getting file system permissions and implement ↵Aaron Ballman2017-03-135-55/+304
| | | | | | | | sys::fs::permissions to set them. Patch by James Henderson. llvm-svn: 297617
* [AArch64] Map Sched Read/Write resources for Falkor.Balaram Makam2017-03-131-1/+183
| | | | llvm-svn: 297611
* [LV] Set memcheck metadata also for VF==1Gil Rapaport2017-03-131-5/+1
| | | | | | | | This commit is a follow-up on r297580. It fixes the FIXME added temporarily by that commit to keep the removal of Unroller's specialized version of scalarizeInstruction() an NFC. See https://reviews.llvm.org/D30715 for details. llvm-svn: 297610
* ARMDisassembler: loop over ARM decode tablesSjoerd Meijer2017-03-131-57/+20
| | | | | | | | | Loop over the ARM decode tables; this is a clean-up to reduce some code duplication. Differential Revision: https://reviews.llvm.org/D30814 llvm-svn: 297608
* AMDGPU/RelocVisitor: Handle R_AMDGPU_ABS64Konstantin Zhuravlyov2017-03-131-0/+7
| | | | | | | | Test is in the separate patch. Differential Revision: https://reviews.llvm.org/D30027 llvm-svn: 297604
* [AVX-512] Add EVEX2VEX test cases for the cvt instructions fixed in r297599 ↵Craig Topper2017-03-131-0/+20
| | | | | | and r297600. llvm-svn: 297603
* Revert "[AVX-512] EVEX2VEX, don't reject intrinsic instructions when both ↵Craig Topper2017-03-132-7/+6
| | | | | | | | | | have a memory operand. We should just continue to check other operands instead." This reverts r297596. There were other issues that were making this not work that have been fixed now. Reverting this results in a more accurate table. llvm-svn: 297602
* [AVX-512] Add VEX_WIG to VEX vcvtsd2ss/vcvtss2sd intrinsic instructions so ↵Craig Topper2017-03-131-8/+8
| | | | | | they can be correctly matched by EVEX2VEX table generation. llvm-svn: 297601
* [AVX-512] Use sse_loadf32/f64 for vcvtss2sd and vcvtsd2ss intrinsic patterns.Craig Topper2017-03-131-3/+2
| | | | llvm-svn: 297600
* [AVX-512] Use sse_load_f64/f32 in VCVTSS2SI/VCVTSD2SI patterns.Craig Topper2017-03-131-10/+10
| | | | llvm-svn: 297599
* [AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a ↵Craig Topper2017-03-132-6/+7
| | | | | | | | memory operand. We should just continue to check other operands instead. This exposed that we have several intrinsic instructions that have identical TSFlags to other instructions. We should merge their patterns and kill of the duplicate. I'll fix that in a follow up patch. llvm-svn: 297596
* [X86] Minor formatting tweaks in EVEX to VEX tables. NFCCraig Topper2017-03-131-45/+45
| | | | llvm-svn: 297595
* [X86] Remove unused SDTypeProfile. NFCCraig Topper2017-03-121-2/+0
| | | | llvm-svn: 297594
* [X86] Lower SSE/AVX cmpps/pd intrinsics directly to X86ISD::CMPP SDNodes.Craig Topper2017-03-123-46/+17
| | | | | | This allows us to remove a duplicate set of patterns. llvm-svn: 297593
* [AVX-512] Fix the valid immediates for the scatter/gather prefetch intrinsics.Craig Topper2017-03-122-6/+7
| | | | | | The immediate should be 1 or 2, not 0 or 1. This was found while adding bounds checking to clang. In fact the existing clang builtin test failed if we ran it all the way to assembly. llvm-svn: 297591
* [x86] don't blindly transform SETB into SBBSanjay Patel2017-03-1216-191/+220
| | | | | | | | | | | | | | | | | | | | I noticed unnecessary 'sbb' instructions in D30472 and while looking at 'ptest' codegen recently. This happens because we were transforming any 'setb' - even when we only wanted a single-bit result. This patch moves those transforms under visitAdd/visitSub, so we we're only creating sbb/adc when it is a win. I don't know why we need a SETCC_CARRY node type, but I'm not proposing to change that existing behavior in this patch. Also, I'm skeptical that sbb/adc are a win for all micro-arches, so I added comments to the test files where this transform still fires. The test changes here are all cases where we no longer produce sbb/adc. Avoiding partial register stalls (generating an xor to clear a register) is not handled in some cases, but that's a separate issue. Differential Revision: https://reviews.llvm.org/D30611 llvm-svn: 297586
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