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* [MC][mips] Add MipsMCInstrAnalysis class and register it as MC instruction ↵Simon Atanasyan2016-03-242-0/+72
| | | | | | | | | | | | | analyzer The `MipsMCInstrAnalysis` class overrides the `evaluateBranch` method and calculates target addresses for branch and calls instructions. That allows llvm-objdump to print functions' names in branch instructions in the disassemble mode. Differential Revision: http://reviews.llvm.org/D18209 llvm-svn: 264309
* Remove unnecessary redirect from testSanjoy Das2016-03-241-2/+2
| | | | llvm-svn: 264308
* reorganize llc checks script to allow more flexibility, part 2; NFCISanjay Patel2016-03-241-73/+104
| | | | | | | | The goal is to enhance this script to be used with opt and clang: Break 'main' into functions and change variable names to be more generic because we want to handle more than x86 asm output. llvm-svn: 264307
* Fix gold tests for llvm-readobj format change.Rafael Espindola2016-03-242-4/+6
| | | | llvm-svn: 264306
* [X86][XOP] Fixed instruction postfixes to more closely match operandsSimon Pilgrim2016-03-242-91/+91
| | | | | | Suggested by Sanjay in D18189 as the multiple folding options in XOP instructions can be tricky llvm-svn: 264305
* BitcodeWriter: Move abbreviation for GenericDINode; almost NFCDuncan P. N. Exon Smith2016-03-243-21/+19
| | | | | | | | | | | | Simplify ValueEnumerator and WriteModuleMetadata by shifting the logic for the METADATA_GENERIC_DEBUG abbreviation into WriteGenericDINode. (This is just like r264302, but for GenericDINode.) The only change is that the abbreviation is emitted later in the bitcode, just before the first `GenericDINode` record. This shouldn't be observable though. llvm-svn: 264303
* BitcodeWriter: Move abbreviation for DILocation; almost NFCDuncan P. N. Exon Smith2016-03-243-20/+18
| | | | | | | | | | | Simplify ValueEnumerator and WriteModuleMetadata by shifting the logic for the METADATA_LOCATION abbreviation into WriteDILocation. The only change is that the abbreviation is emitted later in the bitcode, just before the first `DILocation` record. This shouldn't be observable though. llvm-svn: 264302
* BitcodeWriter: Split out named metadata; almost NFCDuncan P. N. Exon Smith2016-03-241-25/+31
| | | | | | | | | | | | Split writeNamedMetadata out of WriteModuleMetadata to write named metadata, and createNamedMetadataAbbrev for the abbreviation. There should be no effective functionality change, although the layout of the bitcode will change. Previously, the abbreviation was emitted at the top of the block, but now it is delayed until immediately before the named metadata records are emitted. llvm-svn: 264301
* [llvm-readobj] Decode st_other symbol's flagsSimon Atanasyan2016-03-2412-18/+102
| | | | | | | | | The patch supports common STV_xxx visibility flags and MIPS specific STO_MIPS_xxx flags. Differential Revision: http://reviews.llvm.org/D18447 llvm-svn: 264300
* Bitcode: Module* -> Module&, NFCDuncan P. N. Exon Smith2016-03-241-5/+5
| | | | llvm-svn: 264299
* AVX-512: Generate KTEST instead of TEST fir i1 vectorsElena Demikhovsky2016-03-242-7/+138
| | | | | | | | | | | | KTEST instruction may be used instead of TEST in this case: %int_sel3 = bitcast <8 x i1> %sel3 to i8 %res = icmp eq i8 %int_sel3, zeroinitializer br i1 %res, label %L2, label %L1 Differential Revision: http://reviews.llvm.org/D18444 llvm-svn: 264298
* ErrorTest.cpp: Move instantiations out of anonymous namespace. gcc didn't ↵NAKAMURA Takumi2016-03-241-4/+3
| | | | | | complain. llvm-svn: 264297
* CodeGen: extend RHS when splitting ATOMIC_CMP_SWAP_WITH_SUCCESS.Tim Northover2016-03-244-5/+79
| | | | | | | | | | | | | If the operation's type has been promoted during type legalization, we need to account for the fact that the high bits of the comparison operand are likely unspecified. The LHS is usually zero-extended, but MIPS sign extends it, so we have to be slightly careful. Patch by Simon Dardis. llvm-svn: 264296
* AMDGPU/SI: Add Polaris supportTom Stellard2016-03-241-0/+8
| | | | | | Patch By: Sonny Jiang llvm-svn: 264295
* [X86][XOP] Merged 128/256 bit 4op instruction definitions. NFCI.Simon Pilgrim2016-03-241-15/+14
| | | | llvm-svn: 264294
* Define ErrorInfo::ID explicitly.NAKAMURA Takumi2016-03-243-3/+7
| | | | llvm-svn: 264293
* Fix another case where we were unconditionally linking linkonce GVs.Rafael Espindola2016-03-243-0/+24
| | | | | | | With this I think that now llvm-link, lld and the gold plugin should agree on which symbol is kept. llvm-svn: 264292
* Error.cpp: Fix a warning. [-Wpedantic]NAKAMURA Takumi2016-03-241-1/+1
| | | | llvm-svn: 264291
* ErrorTest.cpp: Fix an expression, possibly typo.NAKAMURA Takumi2016-03-241-1/+1
| | | | llvm-svn: 264290
* Fix resolution of linkonce symbols in comdats.Rafael Espindola2016-03-243-2/+23
| | | | | | | | | | | After comdat processing, the symbols still go through regular symbol resolution. We were not doing it for linkonce symbols since they are lazy linked. This fixes pr27044. llvm-svn: 264288
* [mips] Range check vsplat_simm5 and vsplat_simm10Daniel Sanders2016-03-243-213/+262
| | | | | | | | | | | | Summary: Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18177 llvm-svn: 264287
* Remove unsafe AssertZext after promoting result of FP_TO_FP16Pirama Arumuga Nainar2016-03-242-4/+13
| | | | | | | | | | | | | | | Summary: Some target lowerings of FP_TO_FP16, for instance ARM's vcvtb.f16.f32 instruction, do not guarantee that the top 16 bits are zeroed out. Remove the unsafe AssertZext and add tests to exercise this. Reviewers: jmolloy, sbaranga, kristof.beyls, aadg Subscribers: llvm-commits, srhines, aemerson Differential Revision: http://reviews.llvm.org/D18426 llvm-svn: 264285
* [PowerPC] Disable direct moves for extractelement and bitcast in 32-bit modeNemanja Ivanovic2016-03-242-2/+17
| | | | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D17711 It disables direct moves on these operations in 32-bit mode since the patterns assume 64-bit registers. The final patch is slightly different from the Phabricator review as the bitcast operations needed to be disabled in 32-bit mode as well. This fixes PR26617. llvm-svn: 264282
* Recommitted r263424 "Supporting all entities declared in lexical scope in ↵Amjad Aboud2016-03-2421-91/+916
| | | | | | | | | | LLVM debug info." After fixing PR26942 (the fix is included in this commit). Differential Revision: http://reviews.llvm.org/D18350 llvm-svn: 264280
* [mips] Range check simm10Daniel Sanders2016-03-244-4/+17
| | | | | | | | | | | | Summary: Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18148 llvm-svn: 264279
* [X86][XOP] Support for VPPERM byte shuffle instructionSimon Pilgrim2016-03-246-5/+60
| | | | | | | | This patch begins adding support for lowering to the XOP VPPERM instruction - adding the X86ISD::VPPERM opcode. Differential Revision: http://reviews.llvm.org/D18189 llvm-svn: 264260
* [mips] Tidy up cnMIPS tablegen definitions. NFC.Daniel Sanders2016-03-242-51/+58
| | | | | | | | | | | | | | | | | | | Summary: In particular, make the cnMIPS predicates much more obvious and prefer def ... : ... { let Foo = bar; } over: let Foo = bar in def ... : ...; Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18354 llvm-svn: 264258
* Fix sequence point warning. NFC.Vasileios Kalintiris2016-03-241-1/+1
| | | | llvm-svn: 264255
* [llvm-nm] Fix r264247James Molloy2016-03-241-1/+1
| | | | | | I committed the test changes successfully but managed to miss the actual code change! (lack of git -a) llvm-svn: 264249
* [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, ↵Zlatko Buljan2016-03-2415-59/+655
| | | | | | | | DDIVU and DMODU instructions Differential Revision: http://reviews.llvm.org/D17137 llvm-svn: 264248
* [llvm-nm] Correct -P ELF outputJames Molloy2016-03-242-0/+4
| | | | | | Correctly add a space between the address and size when outputting in posix mode (-P). llvm-svn: 264247
* [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructionsHrvoje Varga2016-03-2415-11/+248
| | | | | | Differential Revision: http://reviews.llvm.org/D17328 llvm-svn: 264246
* [mips][microMIPS] Fix for "Cannot copy registers" assertionHrvoje Varga2016-03-246-9/+26
| | | | | | Differential Revision: http://reviews.llvm.org/D17068 llvm-svn: 264245
* [LAA] Formatting fix in previous changeAdam Nemet2016-03-241-2/+1
| | | | llvm-svn: 264244
* [LAA] Support memchecks involving loop-invariant addressesAdam Nemet2016-03-242-17/+69
| | | | | | | | | | | | | | | | | | | | We used to only allow SCEVAddRecExpr for pointer expressions in order to be able to compute the bounds. However this is also trivially possible for loop-invariant addresses (scUnknown) since then the bounds are the address itself. Interestingly, we used allow this for the special case when the loop-invariant address happens to also be an SCEVAddRecExpr (in an outer loop). There are a couple more loops that are vectorized in SPEC after this. My guess is that the main reason we don't see more because for example a loop-invariant load is vectorized into a splat vector with several vector-inserts. This is likely to make the vectorization unprofitable. I.e. we don't notice that a later LICM will move all of this out of the loop so the cost estimate should really be 0. llvm-svn: 264243
* [Support] Add conversions between Expected<T> and ErrorOr<T>.Lang Hames2016-03-242-1/+40
| | | | | | More utilities to help with std::error_code -> Error transitions. llvm-svn: 264238
* [libFuzzer] don't report memory leaks if we are dying due to a timeout (just ↵Kostya Serebryany2016-03-245-5/+25
| | | | | | use _Exit instead of exit in the timeout callback) llvm-svn: 264237
* [libFuzzer] use fdopen+vfprintf instead of fsnprintf+writeKostya Serebryany2016-03-241-11/+10
| | | | llvm-svn: 264230
* [X86][SSE] Added tests to ensure that consecutive loads including any/all ↵Simon Pilgrim2016-03-243-0/+275
| | | | | | volatiles are not combined llvm-svn: 264225
* [PS4] Guarantee an instruction after a 'noreturn' call.Paul Robinson2016-03-243-1/+45
| | | | | | | | | | We need the "return address" of a noreturn call to be within the bounds of the calling function; TrapUnreachable turns 'unreachable' into a 'ud2' instruction, which has that desired effect. Differential Revision: http://reviews.llvm.org/D18414 llvm-svn: 264224
* Fix lazy linking of comdat members.Rafael Espindola2016-03-242-15/+17
| | | | | | | | | | | If not for lazy linking of linkonce GVs, comdats are just a preprocessing before symbol resolution. Lazy linking complicates it since when we pick a visible member of comdat, we have to make sure the rest of it passes symbol resolution too. llvm-svn: 264223
* [sancov] -print-coverage-stats option to print various coverage statistics.Mike Aizatsky2016-03-242-4/+59
| | | | | | Differential Revision: http://reviews.llvm.org/D18418 llvm-svn: 264222
* [Support] Make all Errors convertible to std::error_code.Lang Hames2016-03-235-5/+68
| | | | | | | | | | | | This is a temporary crutch to enable code that currently uses std::error_code to be incrementally moved over to Error. Requiring all Error instances be convertible enables clients to call errorToErrorCode on any error (not just ECErrors created by conversion *from* an error_code). This patch also moves code for Error from ErrorHandling.cpp into a new Error.cpp file. llvm-svn: 264221
* APFloat: Fix signalling nans for scalbnMatt Arsenault2016-03-232-1/+18
| | | | llvm-svn: 264219
* AMDGPU: Remove atomic inc/dec patternsMatt Arsenault2016-03-233-139/+116
| | | | | | | There is no benefit to these since materializing the constant 1 requires the same number of instructions as materializing uint_max llvm-svn: 264215
* AMDGPU: Promote alloca should skip volatilesMatt Arsenault2016-03-232-0/+39
| | | | llvm-svn: 264214
* [sancov] code readability improvement.Mike Aizatsky2016-03-231-11/+26
| | | | | | | | Summary: Reply to http://reviews.llvm.org/D18341 Differential Revision: http://reviews.llvm.org/D18406 llvm-svn: 264213
* docs: Fix a missing language in a code-blockJustin Bogner2016-03-231-1/+1
| | | | | | | This should fix the docs build. Spotted by spstarr, thanks! llvm-svn: 264209
* [CUDA] Update docs to reflect that we no longer define __NVCC__.Justin Lebar2016-03-231-4/+5
| | | | llvm-svn: 264208
* StringRef::copy shouldn't allocate anything for length 0 strings.Pete Cooper2016-03-232-0/+12
| | | | | | | | | | | The BumpPtrAllocator currently doesn't handle zero length allocations well. The discussion for how to fix that is ongoing. However, there's no need for StringRef::copy to actually allocate anything here anyway, so just return StringRef() when we get a zero length copy. Reviewed by David Blaikie llvm-svn: 264201
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