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* [TableGen] Remove constant string argument from a method that's only called ↵Craig Topper2016-02-141-5/+5
| | | | | | once. We can just hardcode the string inside. There already other things that make the method not reusable. NFC llvm-svn: 260840
* [PM/AA] Wire BasicAA's new pass manager class up to the pass registry.Chandler Carruth2016-02-134-3/+13
| | | | | | | | This ensures that all of the various pieces are working. The next patch will wire up commandline-driven alias analysis chain building and allow BasicAA to work with the AAManager. llvm-svn: 260838
* [PM/AA] Actually wire the AAManager I built for the new pass managerChandler Carruth2016-02-135-2/+23
| | | | | | | | | | | | into the new pass manager and fix the latent bugs there. This lets everything live together nicely, but it isn't really useful yet. I never finished wiring the AA layer up for the new pass manager, and so subsequent patches will change this to do that wiring and get AA stuff more fully integrated into the new pass manager. Turns out this is necessary even to get functionattrs ported over. =] llvm-svn: 260836
* Support: Fix incremental build when re-configuring targetsDuncan P. N. Exon Smith2016-02-134-40/+67
| | | | | | | | | | | | | | r180893 added an indirect include of llvm/Config/Targets.def to llvm/Support/CodeGen.h, which in turn is included by things like llvm/IR/Module.h. After a full build of LLVM and Clang, ninja had to rebuild 1274 files after reconfiguring. This commit strips CodeGen.h back down to just a pile of enums and moves the expensive includes over to CodeGenCWrappers.h (which is only included in two places). This gets ninja down to 88 files if you reconfigure with, e.g., -DLLVM_TARGETS_TO_BUILD=X86. llvm-svn: 260835
* [X86][AVX] Lower shuffles as repeated lane shuffles then lane-crossing shufflesSimon Pilgrim2016-02-139-119/+256
| | | | | | | | | | | | | | | | | | This patch attempts to represent a shuffle as a repeating shuffle (recognisable by is128BitLaneRepeatedShuffleMask) with the source input(s) in their original lanes, followed by a single permutation of the 128-bit lanes to their final destinations. On AVX2 we can additionally attempt to match using 64-bit sub-lane permutation. AVX2 can also now match a similar 'broadcasted' repeating shuffle. This patch has several benefits: * Avoids prematurely matching with lowerVectorShuffleByMerging128BitLanes which can require both inputs to have their input lanes permuted before shuffling. * Can replace PERMPS/PERMD instructions - although these are useful for cross-lane unary shuffling, they require their shuffle mask to be pre-loaded (and increase register pressure). * Matching the repeating shuffle makes use of a lot of existing shuffle lowering. There is an outstanding minor AVX1 regression (combine_unneeded_subvector1 in vector-shuffle-combining.ll) of a previously 128-bit shuffle + subvector splat being converted to a subvector splat + (2 instruction) 256-bit shuffle, I intend to fix this in a followup patch for review. Differential Revision: http://reviews.llvm.org/D16537 llvm-svn: 260834
* Remove Proc feature flags for X86 processors that are used to inherit ↵Craig Topper2016-02-132-38/+34
| | | | | | features from one processor to another. This exposed extra features to the -mattr command line that we shouldn't. Replace with just inherited listconcats. llvm-svn: 260832
* [TableGen] Fix comment about 64-bit type I missed when I removed the ↵Craig Topper2016-02-131-1/+1
| | | | | | underlying type in r260808. llvm-svn: 260830
* [libFuzzer] remove std::vector operations from hot paths, NFCKostya Serebryany2016-02-135-31/+38
| | | | llvm-svn: 260829
* [x86-64] allow mfence even with -mno-sse (PR23203)Sanjay Patel2016-02-135-15/+42
| | | | | | | | | | | | | As shown in: https://llvm.org/bugs/show_bug.cgi?id=23203 ...we currently die because lowering believes that mfence is allowed without SSE2 on x86-64, but the instruction def doesn't know that. I don't know if allowing mfence without SSE is right, but if not, at least now it's consistently wrong. :) Differential Revision: http://reviews.llvm.org/D17219 llvm-svn: 260828
* [APInt] No need for a copy when taking min/max of an APInt.Benjamin Kramer2016-02-131-4/+12
| | | | llvm-svn: 260827
* [ConstantFolding] Reduce APInt and APFloat copying.Benjamin Kramer2016-02-132-8/+8
| | | | llvm-svn: 260826
* [AggressiveAntiDepBreaker] Skip some unnecessary BitVector copies.Benjamin Kramer2016-02-131-9/+11
| | | | llvm-svn: 260825
* Use ArrayRef to hide SmallVector details, kill a useless vector copy along ↵Benjamin Kramer2016-02-131-3/+2
| | | | | | the way. llvm-svn: 260824
* [Hexagon] Replace use of "std::map::emplace" with "insert"Krzysztof Parzyszek2016-02-131-1/+4
| | | | | | | Gcc 4.7.2-4 does not seem to have "emplace" in its implementation of map. This should fix the build failure on polly-amd64-linux. llvm-svn: 260816
* [attrs] Move the norecurse deduction to operate on the node set ratherChandler Carruth2016-02-134-21/+28
| | | | | | | | | | | | | | | | | | than the SCC object, and have it scan the instruction stream directly rather than relying on call records. This makes the behavior of this routine consistent between libc routines and LLVM intrinsics for libc routines. We can go and start teaching it about those being norecurse, but we should behave the same for the intrinsic and the libc routine rather than differently. I chatted with James Molloy and the inconsistency doesn't seem intentional and likely is due to intrinsic calls not being modelled in the call graph analyses. This also fixes a bug where we would deduce norecurse on optnone functions, when generally we try to handle optnone functions as-if they were replaceable and thus unanalyzable. llvm-svn: 260813
* HexagonFrameLowering.cpp: Appease msc18 to give an explicit constructor ↵NAKAMURA Takumi2016-02-131-2/+4
| | | | | | SlotInfo() instead of member initializers. llvm-svn: 260812
* [libFuzzer] don't require seed in fuzzer::Mutate, instead use the global ↵Kostya Serebryany2016-02-135-12/+21
| | | | | | Fuzzer object for fuzzer::Mutate. This makes custom mutators fast llvm-svn: 260810
* [TableGen] Use range-based for loops. NFCCraig Topper2016-02-132-131/+106
| | | | llvm-svn: 260809
* No need to make the subtarget feature bit enum a uint64_t. This was a ↵Craig Topper2016-02-131-1/+1
| | | | | | leftover from when the feature bit enum contained masks instead of bit indices. llvm-svn: 260808
* LiveIntervalAnalysis: Remove LiveVariables requirementMatthias Braun2016-02-133-7/+3
| | | | | | | | | This requirement was a huge hack to keep LiveVariables alive because it was optionally used by TwoAddressInstructionPass and PHIElimination. However we have AnalysisUsage::addUsedIfAvailable() which we can use in those passes. llvm-svn: 260806
* AMDGPU: Prepare for reducing private element size.Matt Arsenault2016-02-134-16/+179
| | | | | | | | | | | | Tests for the new scalarize all private access options will be included with a future commit. The only functional change is to make the split/scalarize behavior for private access of > 4 element vectors to be consistent with the flat/global handling. This makes the spilling worse in the two changed tests. llvm-svn: 260804
* [libFuzzer] remove the C++-ish variant of FuzzerDriver from the interfaceKostya Serebryany2016-02-132-12/+7
| | | | llvm-svn: 260801
* [libFuzzer] simplify CTOR of MutationDispatcherKostya Serebryany2016-02-132-21/+21
| | | | llvm-svn: 260800
* [libFuzzer] get rid of MutationDispatcher::Impl (simplify the code; NFC)Kostya Serebryany2016-02-132-136/+114
| | | | llvm-svn: 260799
* [libFuzzer] get rid of UserSuppliedFuzzer; NFCKostya Serebryany2016-02-139-97/+41
| | | | llvm-svn: 260798
* [libFuzzer] simplify the code around Random. NFCKostya Serebryany2016-02-135-87/+39
| | | | llvm-svn: 260797
* [libFuzzer] remove UserSuppliedFuzzer from the interface (it was a bad idea).Kostya Serebryany2016-02-136-160/+68
| | | | llvm-svn: 260796
* [libFuzzer] provide a plain C interface for custom mutators (experimental)Kostya Serebryany2016-02-136-2/+65
| | | | llvm-svn: 260794
* AMDGPU/SI: Add llvm.amdgcn.mov.dpp intrinsicTom Stellard2016-02-133-0/+30
| | | | | | | This intrinsic will be used to expose dpp functionality to higher-level languages. It will map to the dpp version of v_mov_b32. llvm-svn: 260792
* [Cloning] Clone every Function's Debug InfoKeno Fischer2016-02-134-2/+33
| | | | | | | | | | | | | | | | | | | | | | | Summary: Export the CloneDebugInfoMetadata utility, which clones all debug info associated with a function into the first module. Also use this function in CloneModule on each function we clone (the CloneFunction entrypoint already does this). Without this, cloning a module will lead to DI quality regressions, especially since r252219 reversed the Function <-> DISubprogram edge (before we could get lucky and have this edge preserved if the DISubprogram itself was, e.g. due to location metadata). This was verified to fix missing debug information in julia and a unittest to verify the new behavior is included. Patch by Yichao Yu! Thanks! Reviewers: loladiro, pcc Differential Revision: http://reviews.llvm.org/D17165 llvm-svn: 260791
* Add AMDGPU related triple vendors/OSesMatt Arsenault2016-02-133-2/+23
| | | | | | | | As support expands to more runtimes, we'll need to distinguish between more than just HSA and unknown. This also lets us stop using unknown everywhere. llvm-svn: 260790
* [llvm-size] Remove variable used only once.Davide Italiano2016-02-131-8/+4
| | | | | | The use of auto and the name were very weird anyway. llvm-svn: 260789
* [llvm-size] Make error handling uniform.Davide Italiano2016-02-132-33/+10
| | | | llvm-svn: 260786
* AMDGPU: Cleanup includes and random macrosMatt Arsenault2016-02-131-11/+4
| | | | llvm-svn: 260784
* AMDGPU: Add intrinsics for sin/cosMatt Arsenault2016-02-136-1/+77
| | | | | | | These provide direct access to the hardware instruction without the unit version required like llvm.sin/llvm.cos lowering requires. llvm-svn: 260782
* AMDGPU: Rename intrinsic to better match instruction nameMatt Arsenault2016-02-1310-33/+53
| | | | | | Also fixes missing f32 test. llvm-svn: 260780
* AMDGPU/SI: Add instruction defs for VOP1 DPP instructionsTom Stellard2016-02-132-0/+107
| | | | | | | | | | Reviewers: nhaustov, cfang, arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D17159 llvm-svn: 260774
* AMDGPU: Fix broken condition causing warningMatt Arsenault2016-02-131-1/+1
| | | | llvm-svn: 260773
* AMDGPU/SI: Organize intrinsics by subtargetTom Stellard2016-02-131-20/+25
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D17210 llvm-svn: 260771
* Don't combine fp_round (fp_round x) if f80 to f16 is generatedPirama Arumuga Nainar2016-02-132-0/+26
| | | | | | | | | | | | | | | | | | | | Summary: This patch skips DAG combine of fp_round (fp_round x) if it results in an fp_round from f80 to f16. fp_round from f80 to f16 always generates an expensive (and as yet, unimplemented) libcall to __truncxfhf2. This prevents selection of native f16 conversion instructions from f32 or f64. Moreover, the first (value-preserving) fp_round from f80 to either f32 or f64 may become a NOP in platforms like x86. Reviewers: ab Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D17221 llvm-svn: 260769
* Fix Windows buildbot breakage.Alexey Samsonov2016-02-121-3/+4
| | | | llvm-svn: 260766
* AMDGPU/SI: Detect uniform branches and emit s_cbranch instructionsTom Stellard2016-02-1235-119/+937
| | | | | | | | | | Reviewers: arsenm Subscribers: mareko, MatzeB, qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D16603 llvm-svn: 260765
* Disable the vzeroupper insertion pass on PS4.Yunzhong Gao2016-02-125-2/+19
| | | | | | Differential Revision: http://reviews.llvm.org/D16837 llvm-svn: 260764
* cmake: Simplify the iOS.cmake toolchainJustin Bogner2016-02-121-40/+15
| | | | | | | | | | | | | | | - Remove a comment that was clearly copy pasted from Android.cmake and isn't relevant. - Remove the toolchain's sensitivity to the environment. It's less error prone to just allow users to set CMAKE_OSX_SYSROOT if they want to use a custom SDK. - Stop explicitly setting -mios-version-min to the default value. It just adds needless complexity. This makes building the native tablegen work for me even when SDKROOT is set in the environment (or passed in as -DCMAKE_OSX_SYSROOT). llvm-svn: 260763
* [WebAssembly] Report more meaningful error messages for some unsupportedDerek Schuff2016-02-122-4/+17
| | | | | | | | | ops. Computed gotos and RETURNADDR may never be supported; we can do FRAMEADDR in the future. llvm-svn: 260759
* [Hexagon] Optimize stack slot spillsKrzysztof Parzyszek2016-02-1210-6/+1442
| | | | | | | | | | | | | | Replace spills to memory with spills to registers, if possible. This applies mostly to predicate registers (both scalar and vector), since they are very limited in number. A spill of a predicate register may happen even if there is a general-purpose register available. In cases like this the stack spill/reload may be eliminated completely. This optimization will consider all stack objects, regardless of where they came from and try to match the live range of the stack slot with a dead range of a register from an appropriate register class. llvm-svn: 260758
* [llvm-pdbdump] Start to decode some streamsDavid Majnemer2016-02-122-29/+278
| | | | | | We can decode a little bit of the first stream now. llvm-svn: 260754
* [Hexagon] Mark HVX registers as volatileKrzysztof Parzyszek2016-02-121-1/+7
| | | | llvm-svn: 260753
* fix test to use FileCheckSanjay Patel2016-02-121-3/+6
| | | | llvm-svn: 260751
* [WebAssembly] Update test expectations after r260737Derek Schuff2016-02-121-13/+1
| | | | llvm-svn: 260750
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