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* Masked Load/Store optimization for scalar codeElena Demikhovsky2015-10-212-12/+109
| | | | | | | | | When we have to convert the masked.load, masked.store to scalar code, we generate a chain of conditional basic blocks. I added optimization for constant mask vector. Differential Revision: http://reviews.llvm.org/D13855 llvm-svn: 250893
* [mips][msa] Remove copy_u.d and move copy_u.w to MSA64.Daniel Sanders2015-10-218-48/+51
| | | | | | | | | | | | | | | | | | | | | | | Summary: The forwards compatibility strategy employed by MIPS is to consider registers to be infinitely sign-extended. Then on ISA's with a wider register, the result of existing instructions are sign-extended to register width and zero-extended counterparts are added. copy_u.w on MSA32 and copy_u.w on MSA64 violate this strategy and we have therefore corrected the MSA specs to fix this. We still keep track of sign/zero-extension during legalization but we now match copy_s.[wd] where required. No change required to clang since __builtin_msa_copy_u_[wd] will map to copy_s.[wd] where appropriate for the target. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13472 llvm-svn: 250887
* Let MachineVerifier be aware of mem-to-mem instructions.Jonas Paulsson2015-10-212-3/+9
| | | | | | | | | | | | | | | A mem-to-mem instruction (that both loads and stores), which store to an FI, cannot pass the verifier since it thinks it is loading from the FI. For the mem-to-mem instruction, do a looser check in visitMachineOperand() and only check liveness at the reg-slot while analyzing a frame index operand. Needed to make CodeGen/SystemZ/xor-01.ll pass with -verify-machineinstrs, which now runs with this flag. Reviewed by Evan Cheng and Quentin Colombet. llvm-svn: 250885
* Do not use `dyn_cast<X>` after `isa<X>` (NFC)Mehdi Amini2015-10-211-1/+1
| | | | | From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 250883
* Revert "Add missing #include, found by modules build."Mehdi Amini2015-10-212-83/+8
| | | | | | | | | | | This reverts commit r250239. It seems unwanted changes got committed here, and part of the patch does not seem correct. For instance RoundUpToAlignment() is called without its returned value actually used. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 250882
* Tail duplication can mix incompatible registers in phi nodesKrzysztof Parzyszek2015-10-212-0/+49
| | | | | | | | | Do not tail duplicate blocks where the successor has a phi node, and the corresponding value in that phi node uses a subregister. http://reviews.llvm.org/D13922 llvm-svn: 250877
* WebAssembly: support importsJF Bastien2015-10-212-1/+44
| | | | | | C/C++ code can declare an extern function, which will show up as an import in WebAssembly's output. It's expected that the linker will resolve these, and mark unresolved imports as call_import (I have a patch which does this in wasmate). llvm-svn: 250875
* Tolerate negative offset when matching sample profile.Dehao Chen2015-10-214-10/+117
| | | | | | | | In some cases (as illustrated in the unittest), lineno can be less than the heade_lineno because the function body are included from some other files. In this case, offset will be negative. This patch makes clang still able to match the profile to IR in this situation. http://reviews.llvm.org/D13914 llvm-svn: 250873
* [Hexagon] Bit-based instruction simplificationKrzysztof Parzyszek2015-10-209-4/+2930
| | | | | | | Analyze bit patterns of operands and values of instructions to perform various simplifications, dead/redundant code elimination, etc. llvm-svn: 250868
* [Hexagon] Fix isNVStorable flag in .td filesKrzysztof Parzyszek2015-10-202-20/+48
| | | | | | | An upper half and a double word cannot be used as value sources in a new-value store. llvm-svn: 250867
* [MemorySanitizer] NFC. Do not use GET_INTRINSIC_MODREF_BEHAVIOR table.Igor Laevsky2015-10-201-28/+3
| | | | | | | | | It is now possible to infer intrinsic modref behaviour purely from intrinsic attributes. This change will allow to completely remove GET_INTRINSIC_MODREF_BEHAVIOR table. Differential Revision: http://reviews.llvm.org/D13907 llvm-svn: 250860
* [X86][SSE] Add 256-bit vector bit rotation tests.Simon Pilgrim2015-10-201-0/+1200
| | | | llvm-svn: 250853
* bugpoint: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-203-56/+47
| | | | | | | | This is the last of the implicit ilist iterator conversions in LLVM. Still up for debate whether we let these bitrot back: http://lists.llvm.org/pipermail/llvm-dev/2015-October/091617.html llvm-svn: 250852
* [Hexagon] Capture aggregate variables by reference, not valueKrzysztof Parzyszek2015-10-201-1/+1
| | | | llvm-svn: 250851
* [Hexagon] Do not fall-through if there is no CFG edgeKrzysztof Parzyszek2015-10-201-1/+1
| | | | llvm-svn: 250850
* [Hexagon] Use symbolic name for subregister instead of hardcoded numberKrzysztof Parzyszek2015-10-201-1/+1
| | | | llvm-svn: 250849
* [Hexagon] Change Based->Base in getBasedWithImmOffsetKrzysztof Parzyszek2015-10-202-3/+3
| | | | llvm-svn: 250848
* [Hexagon] Remove the remnants of isConstExtProfitableKrzysztof Parzyszek2015-10-207-125/+27
| | | | llvm-svn: 250845
* unittests: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-2010-53/+52
| | | | llvm-svn: 250843
* llvm-diff: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-201-2/+2
| | | | llvm-svn: 250842
* [CMake] All the checks for if LLVM_VERSION_* variables are set need to be ↵Chris Bieneman2015-10-201-3/+3
| | | | | | | | if(DEFINED ...) This is because if you set one of the variables to 0, if(NOT ...) is true, which isn't what you actually want. Should have thought that through better the first time. llvm-svn: 250841
* [CMake] Refactor subdirectory inclusion code to take a project name.Chris Bieneman2015-10-201-23/+34
| | | | | | | | | | | | | | | Summary: This refactoring makes some of the code used to control including subdirectories parameterized so it can be re-used elsewhere. Specifically I want to re-use this code in clang to be able to turn off specific tool subdirectories. Reviewers: chapuni, filcab, bogner, Bigcheese Subscribers: emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D13783 llvm-svn: 250835
* Two switch blocks in VectorLegalizer::LegalizeOp already have aArtyom Skrobov2015-10-201-0/+1
| | | | | | | | | | default: llvm_unreachable("This action is not supported yet!"); -- so I'm adding one to the third switch block, too. This is a follow-up fix for http://reviews.llvm.org/D13862 llvm-svn: 250830
* [SystemZ] Use LivePhysRegs helper class in SystemZShortenInst.cpp.Jonas Paulsson2015-10-201-80/+35
| | | | | | | | | Don't use home brewed liveness tracking code for phys regs, since this class does the job. Reviewed by Ulrich Weigand. llvm-svn: 250829
* [SystemZ] Comment fix in test/CodeGen/SystemZ/fp-cmp-05.llJonas Paulsson2015-10-201-3/+1
| | | | llvm-svn: 250828
* Adding support for TargetLoweringBase::LibCallArtyom Skrobov2015-10-204-254/+279
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: TargetLoweringBase::Expand is defined as "Try to expand this to other ops, otherwise use a libcall." For ISD::UDIV and ISD::SDIV, the choice between the two possibilities was defined in a rather convoluted way: - if DIVREM is legal, expand to DIVREM - if DIVREM has a custom lowering, expand to DIVREM - if DIVREM libcall is defined and a remainder from the same division is computed elsewhere, expand to a DIVREM libcall - else, expand to a DIV libcall This had the undesirable effect that if both DIV and DIVREM are implemented as libcalls, then ISD::UDIV and ISD::SDIV are expanded to the heavier DIVREM libcall, even when the remainder isn't used. The new code adds a new LegalizeAction, TargetLoweringBase::LibCall, so that backends can directly control whether they prefer an expansion or a conversion to a libcall. This makes the generic lowering code even more generic, allowing its reuse in a wider range of target-specific configurations. The useful effect is that ARM backend will now generate a call to __aeabi_{i,u}div rather than __aeabi_{i,u}divmod in cases where it doesn't need the remainder. There's no functional change outside the ARM backend. Reviewers: t.p.northover, rengolin Subscribers: t.p.northover, llvm-commits, aemerson Differential Revision: http://reviews.llvm.org/D13862 llvm-svn: 250826
* Combining DIV+REM->DIVREM doesn't belong in LegalizeDAG; move it over into ↵Artyom Skrobov2015-10-203-67/+99
| | | | | | | | | | | | | | | | | | | | | | | | DAGCombiner. Summary: In addition to moving the code over, this patch amends the DIV,REM -> DIVREM combining to run on all affected nodes at once: if the nodes are converted to DIVREM one at a time, then the resulting DIVREM may get legalized by the backend into something target-specific that we won't be able to recognize and correlate with the remaining nodes. The motivation is to "prepare terrain" for D13862: when we set DIV and REM to be legalized to libcalls, instead of the DIVREM, we otherwise lose the ability to combine them together. To prevent this, we need to take the DIV,REM -> DIVREM combining out of the lowering stage. Reviewers: RKSimon, eli.friedman, rengolin Subscribers: john.brawn, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D13733 llvm-svn: 250825
* AVX512: Implemented encoding and intrinsics for VPBROADCASTB/W/D/Q instructions.Igor Breger2015-10-2012-121/+1272
| | | | | | Differential Revision: http://reviews.llvm.org/D13884 llvm-svn: 250819
* [x86] Fix AVX maskload/store intrinsic prototypes.Andrea Di Biagio2015-10-204-36/+34
| | | | | | | | | | | | | | | | | | | | | The mask value type for maskload/maskstore GCC builtins is never a vector of packed floats/doubles. This patch fixes the following issues: 1. The mask argument for builtin_ia32_maskloadpd and builtin_ia32_maskstorepd should be of type llvm_v2i64_ty and not llvm_v2f64_ty. 2. The mask argument for builtin_ia32_maskloadpd256 and builtin_ia32_maskstorepd256 should be of type llvm_v4i64_ty and not llvm_v4f64_ty. 3. The mask argument for builtin_ia32_maskloadps and builtin_ia32_maskstoreps should be of type llvm_v4i32_ty and not llvm_v4f32_ty. 4. The mask argument for builtin_ia32_maskloadps256 and builtin_ia32_maskstoreps256 should be of type llvm_v8i32_ty and not llvm_v8f32_ty. Differential Revision: http://reviews.llvm.org/D13776 llvm-svn: 250817
* Fix missing INITIALIZE_PASS_DEPENDENCY for AddressSanitizerKeno Fischer2015-10-201-0/+1
| | | | | | | | | | | | | | Summary: In r231241, TargetLibraryInfoWrapperPass was added to `getAnalysisUsage` for `AddressSanitizer`, but the corresponding `INITIALIZE_PASS_DEPENDENCY` was not added. Reviewers: dvyukov, chandlerc, kcc Subscribers: kcc, llvm-commits Differential Revision: http://reviews.llvm.org/D13629 llvm-svn: 250813
* Make class final to pacify -Wnon-virtual-dtor.Manuel Klimek2015-10-201-1/+1
| | | | llvm-svn: 250805
* AMDGPU: Add MachineInstr overloads for instruction format testsMatt Arsenault2015-10-207-40/+111
| | | | llvm-svn: 250797
* [Orc] Make CompileOnDemandLayer::findSymbol call BaseLayer::findSymbol if noLang Hames2015-10-204-1/+166
| | | | | | symbol definition is found in the logical dylibs. llvm-svn: 250796
* AMDGPU: Stop reserving v[254:255]Matt Arsenault2015-10-202-56/+52
| | | | | | | | | | | This wasn't doing anything useful. They weren't explicitly used anywhere, and the RegScavenger ignores reserved registers. This for some reason caused a random scheduling change in the test. Getting the check lines to pass is too frustrating, and there's probably not too much value in checking the vector case's operands N times. llvm-svn: 250794
* WebAssembly: fix call/return syntax.JF Bastien2015-10-203-4/+19
| | | | | | They are now typeless, unlike other operations. llvm-svn: 250793
* MSP430: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-202-5/+3
| | | | llvm-svn: 250792
* AsmParser: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-201-5/+4
| | | | llvm-svn: 250791
* SystemZ: Remove implicit ilist iterator conversion, NFCDuncan P. N. Exon Smith2015-10-201-1/+1
| | | | llvm-svn: 250790
* XCore: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-202-8/+4
| | | | llvm-svn: 250788
* PowerPC: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-205-27/+23
| | | | llvm-svn: 250787
* [RS4GC] Remove a redundant linear search, NFCISanjoy Das2015-10-201-2/+1
| | | | | | | Since LiveVariables is uniqued (we just created it from a `DenseSet`), `FindIndex(LiveVariables, LiveVariables[i])` is always `i`. llvm-svn: 250786
* [RS4GC] Clean up `find_index`; NFCSanjoy Das2015-10-201-11/+11
| | | | | | | - Bring it up to the LLVM Coding Style - Sink it inside `CreateGCRelocates`, which is its only user llvm-svn: 250785
* [RS4GC] Re-purpose `normalizeForInvokeSafepoint`; NFC.Sanjoy Das2015-10-202-9/+41
| | | | | | | | | | | | `normalizeForInvokeSafepoint` in RewriteStatepointsForGC.cpp, as it is written today, deals with `gc.relocate` and `gc.result` uses of a statepoint equally well. This change documents this fact and adds a test case. There is no functional change here -- only documentation of existing functionality. llvm-svn: 250784
* [RS4GC] Minor cleanup to `normalizeForInvokeSafepoint`; NFCSanjoy Das2015-10-201-3/+3
| | | | llvm-svn: 250783
* Sparc: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-202-5/+4
| | | | llvm-svn: 250781
* NVPTX: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-207-25/+20
| | | | llvm-svn: 250779
* Hexagon: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-2016-38/+34
| | | | | | | | | | | | | | | | | | | There are two things out of the ordinary in this commit. First, I made a loop obviously "infinite" in HexagonInstrInfo.cpp. After checking if an instruction was at the beginning of a basic block (in which case, `break`), the loop decremented and checked the iterator for `nullptr` as the loop condition. This has never been possible (the prev pointers are always been circular, so even with the weird ilist/iplist implementation, this isn't been possible), so I removed the condition. Second, in HexagonAsmPrinter.cpp there was another case of comparing a `MachineBasicBlock::instr_iterator` against `MachineBasicBlock::end()` (which returns `MachineBasicBlock::iterator`). While not incorrect, it's fragile. I switched this to `::instr_end()`. All that said, no functionality change intended here. llvm-svn: 250778
* WebAssembly: fix syntax for br_if.JF Bastien2015-10-204-18/+18
| | | | llvm-svn: 250777
* AsmPrinter: Remove implicit ilist iterator conversion, NFCDuncan P. N. Exon Smith2015-10-201-3/+3
| | | | llvm-svn: 250776
* Mips: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-209-40/+29
| | | | llvm-svn: 250769
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