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* Add a test for i1 zeroext arguments on x86-64. We currently generate code thatCameron Zwarich2011-03-161-0/+23
| | | | | | | conforms to the ABI, but DAGCombine could in theory recognize the sequence of zext asserts and truncates and generate incorrect code. llvm-svn: 127754
* Add checkevent intrinsic to check if any resources owned by the current threadRichard Osborne2011-03-164-55/+160
| | | | | | can event. llvm-svn: 127741
* test/CodeGen/X86: FileCheck-ize and add actions for x86_64-linux and ↵NAKAMURA Takumi2011-03-1610-24/+54
| | | | | | x86_64-win32. llvm-svn: 127734
* test/CodeGen/X86: Add a pattern for Win64.NAKAMURA Takumi2011-03-167-22/+141
| | | | llvm-svn: 127733
* test/CodeGen/X86: FileCheck-ize and add explicit -mtriple=x86_64-linux. They ↵NAKAMURA Takumi2011-03-1612-24/+62
| | | | | | are useless to Win64 target. llvm-svn: 127732
* test/CodeGen/X86/byval*.ll: Win64 has not supported byval yet.NAKAMURA Takumi2011-03-165-9/+102
| | | | llvm-svn: 127731
* test/CodeGen/X86/dyn-stackalloc.ll: FileCheck-ize.NAKAMURA Takumi2011-03-161-3/+6
| | | | llvm-svn: 127730
* Fix a comment.Cameron Zwarich2011-03-161-3/+3
| | | | llvm-svn: 127728
* lib/Support/raw_ostream.cpp: On mingw, report_fatal_error() should not be ↵NAKAMURA Takumi2011-03-161-0/+8
| | | | | | | | called at dtor context. report_fatal_error() invokes exit(). We know report_fatal_error() might not write messages to stderr when any errors were detected on FD == 2. llvm-svn: 127726
* Windows/PathV2.inc: [PR8520] Recognize "NUL" as special (character) file.NAKAMURA Takumi2011-03-161-1/+8
| | | | | FIXME: It is a temporal hack. We should detect as many "special file name" as possible. llvm-svn: 127724
* Windows/Path.inc: [PR6270] PathV1::makeUnique(): Give arbitrary initial seed ↵NAKAMURA Takumi2011-03-161-1/+11
| | | | | | | for workaround. FIXME: We should use sys::fs::unique_file() in future. llvm-svn: 127723
* Tidy up. Whitespace and 80 column.Jim Grosbach2011-03-162-17/+20
| | | | llvm-svn: 127721
* Do not accidently initialize NumDbgValueLost and NumDbgLineLost counts.Devang Patel2011-03-161-4/+4
| | | | llvm-svn: 127720
* Only convert allocas to scalars if it is profitable. The profitability metric ICameron Zwarich2011-03-162-2/+43
| | | | | | | | | | | chose is having a non-memcpy/memset use and being larger than any native integer type. Originally I chose having an access of a size smaller than the total size of the alloca, but this caused some minor issues on the spirit benchmark where SRoA runs again after some inlining. This fixes <rdar://problem/8613163>. llvm-svn: 127718
* Add native integer type TargetData to some existing tests.Cameron Zwarich2011-03-162-2/+2
| | | | llvm-svn: 127717
* Better use initializer lists.Cameron Zwarich2011-03-161-5/+2
| | | | llvm-svn: 127716
* Add a clarifying comment.Cameron Zwarich2011-03-161-1/+1
| | | | llvm-svn: 127715
* Add TargetData::fitsInLegalInteger().Cameron Zwarich2011-03-161-1/+12
| | | | llvm-svn: 127714
* There were two issues fixed:Johnny Chen2011-03-152-13/+12
| | | | | | | | | | | | | | | | 1. The ARM Darwin *r9 call instructions were pseudo-ized recently. Modify the ARMDisassemblerCore.cpp file to accomodate the change. 2. The disassembler was unnecessarily adding 8 to the sign-extended imm24: imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate) // Encoding A1 It has no business doing such. Removed the offending logic. Add test cases to arm-tests.txt. llvm-svn: 127707
* Add scei vendorJohn Thompson2011-03-152-1/+5
| | | | llvm-svn: 127705
* The VTBL (and VTBX) instructions are rather permissive concerning the masks theyBill Wendling2011-03-151-0/+8
| | | | | | | accept. If a value in the mask is out of range, it uses the value 0, for VTBL, or leaves the value unchanged, for VTBX. llvm-svn: 127700
* Trace back through sibling copies to hoist spills and find rematerializable ↵Jakob Stoklund Olesen2011-03-151-10/+208
| | | | | | | | | | | | | defs. After live range splitting, an original value may be available in multiple registers. Tracing back through the registers containing the same value, find the best place to insert a spill, determine if the value has already been spilled, or discover a reaching def that may be rematerialized. This is only the analysis part. The information is not used for anything yet. llvm-svn: 127698
* Preserve both isPHIDef and isDefByCopy bits when copying parent values.Jakob Stoklund Olesen2011-03-151-5/+4
| | | | llvm-svn: 127697
* lit/ProgressBar.py: [PR7919] Improve line wrap for XN-incapable terminals.NAKAMURA Takumi2011-03-151-4/+17
| | | | | | On Win32 console, emitting char to col#79 causes linefeed, and the cursor will not return to col#79 upper line with backspace. llvm-svn: 127696
* Some minor cleanups based on feedback.Bill Wendling2011-03-153-8/+16
| | | | llvm-svn: 127694
* Trailing whitespae.Jim Grosbach2011-03-151-34/+34
| | | | llvm-svn: 127691
* Clean up something noticed by Fritz.Cameron Zwarich2011-03-151-1/+1
| | | | llvm-svn: 127684
* Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587Evan Cheng2011-03-152-9/+58
| | | | llvm-svn: 127683
* Don't indent cases in a switch, no functionality change.Richard Osborne2011-03-151-50/+50
| | | | llvm-svn: 127681
* On the XCore the scavenging slot should be closest to the SP.Richard Osborne2011-03-153-0/+59
| | | | llvm-svn: 127680
* is_llvm_target_library: recognize libraries without the LLVM prefix.Oscar Fuentes2011-03-151-1/+2
| | | | | | | Without this cmake fails at configuration when some target pass "native" on LLVM_LINK_COMPONENTS and that is expanded to "X86". llvm-svn: 127679
* Add XCore intrinsics for getps, setps, setsr and clrsr.Richard Osborne2011-03-154-3/+66
| | | | llvm-svn: 127678
* PTX: Set PTX 2.0 as the minimum supported versionJustin Holewinski2011-03-158-136/+178
| | | | | | | | - Remove PTX 1.4 code generation - Change type of intrinsics to .v4.i32 instead of .v4.i16 - Add and/or/xor integer instructions llvm-svn: 127677
* Silence compiler warning about case values not being in the enumerated typeDuncan Sands2011-03-151-1/+1
| | | | | | MCFixupKind. This is the same technique that is used elsewhere in MC. llvm-svn: 127676
* Avoid a compiler warning about reg possibly being used uninitializedDuncan Sands2011-03-151-4/+2
| | | | | | when building with assertions disabled. llvm-svn: 127675
* Do not add PHIs with no users when creating LCSSA form. Patch by Andrew Clinton.Cameron Zwarich2011-03-153-2/+48
| | | | llvm-svn: 127674
* Add C++ global operator {new,new[],delete,delete[]}(unsigned {int,long}) to theNick Lewycky2011-03-151-2/+11
| | | | | | | | | | | | | memory builtins as equivalent to malloc/free. This is different from any attribute we have. For example, you can delete the allocators when their result is unused, but you can't collapse two calls to the same function, even if no global/memory state has changed in between. The noalias return states that the result does not alias any other pointer, but instcombine optimizes malloc() as though the result is non-null for the purpose of eliminating unused pointers. llvm-svn: 127673
* Add a peephole optimization to optimize pairs of bitcasts. e.g.Evan Cheng2011-03-152-4/+120
| | | | | | | | | | | | | | | | | | | | | | v2 = bitcast v1 ... v3 = bitcast v2 ... = v3 => v2 = bitcast v1 ... = v1 if v1 and v3 are of in the same register class. bitcast between i32 and fp (and others) are often not nops since they are in different register classes. These bitcast instructions are often left because they are in different basic blocks and cannot be eliminated by dag combine. rdar://9104514 llvm-svn: 127668
* - Add "Bitcast" target instruction property for instructions which performEvan Cheng2011-03-156-9/+48
| | | | | | | nothing more than a bitcast. - Teach tablegen to automatically infer "Bitcast" property. llvm-svn: 127667
* PR9450: Make switch optimization in SimplifyCFG not dependent on the orderingEli Friedman2011-03-152-15/+66
| | | | | | of pointers in an std::map. llvm-svn: 127650
* sext(undef) = 0, because the top bits will all be the same.Evan Cheng2011-03-152-3/+7
| | | | | | zext(undef) = 0, because the top bits will be zero. llvm-svn: 127649
* Testcase for r127630.Bill Wendling2011-03-151-0/+18
| | | | llvm-svn: 127648
* Basic sanity checks to ensure that 2- and 3-byteSean Callanan2011-03-151-0/+6
| | | | | | | | VEX prefixes are working for triadic AVX instructions. This concludes the patch set to enable AVX support for the X86 disassebler. llvm-svn: 127647
* Enabled disassembler support for AVX instructionsSean Callanan2011-03-152-150/+152
| | | | | | | | in the instruction tables and fixed a few bugs that were causing decode conflicts. Rudimentary tests are coming up in the next patch. llvm-svn: 127646
* X86 table-generator and disassembler support for the AVXSean Callanan2011-03-157-94/+569
| | | | | | | | | instruction set. This code adds support for the VEX prefix and for the YMM registers accessible on AVX-enabled architectures. Instruction table support that enables AVX instructions for the disassembler is in an upcoming patch. llvm-svn: 127644
* Remove getMinusSCEVForExitTest().Andrew Trick2011-03-151-106/+3
| | | | | | | This function performed acrobatics to prove no-self-wrap, which we now have for free. llvm-svn: 127643
* Fixed an ARM disassembler bug where it does not handle STRi12 correctly ↵Johnny Chen2011-03-152-6/+21
| | | | | | | | | | because an extra register operand was erroneously added. Remove an incorrect assert which triggers the bug. rdar://problem/9131529 llvm-svn: 127642
* There are some situations which can cause the URoR hack to infinitely recurseBill Wendling2011-03-151-6/+8
| | | | | | | | | | | | | and then go kablooie. The problem was that it was tracking the PHI nodes anew each time into this function. But it didn't need to. And because the recursion didn't know that a PHINode was visited before, it would go ahead and call itself. There is a testcase, but unfortunately it's too big to add. This problem will go away with the EH rewrite. <rdar://problem/8856298> llvm-svn: 127640
* Propagate SCEV no-wrap flags whenever possible.Andrew Trick2011-03-154-74/+93
| | | | | | This needs review. llvm-svn: 127638
* Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches.Jim Grosbach2011-03-154-32/+72
| | | | | | | Also more cleanly separate the ARM vs. Thumb functionality. Previously, the encoding would be incorrect for some Thumb instructions (the indirect calls). llvm-svn: 127637
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