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* Handle X86::reloc_riprel_4byte in 32 bits mode.Rafael Espindola2015-03-182-0/+5
| | | | | | | | We can get there with .code64. Fixes pr22349. llvm-svn: 232651
* [Hexagon] Use pseudo-instructions for true/false predicate valuesKrzysztof Parzyszek2015-03-181-23/+6
| | | | llvm-svn: 232650
* Use utils/update_llc_test_checks.py to update all CHECKsSanjay Patel2015-03-181-448/+1384
| | | | | | | | The checks here were so vague that we could nuke intrinsics from existence and still pass the test because we'd match the function name. llvm-svn: 232647
* [Hexagon] Intrinsics for circular and bit-reversed loads and storesKrzysztof Parzyszek2015-03-1811-6/+1306
| | | | llvm-svn: 232645
* fixed to test features, not CPU modelSanjay Patel2015-03-181-4/+5
| | | | | | | | | | | | The 'vmovntdq' was only passing due to a fluke in SandyBridge codegen that splits 32-byte stores in half, but that meant that the test was not correctly checking for the 32-byte store that we thought we were generating. The lax checking in this file will be addressed in another commit. There are bigger problems here. llvm-svn: 232644
* [Hexagon] Handle ENDLOOP0 in InsertBranch and RemoveBranchKrzysztof Parzyszek2015-03-182-20/+30
| | | | llvm-svn: 232643
* Add support for .ifnes psuedo-op.Sid Manning2015-03-183-10/+61
| | | | llvm-svn: 232636
* clang-format these lines to fix Visual C++ warning.Yaron Keren2015-03-181-2/+2
| | | | | | | | | | | | Visual C++ 2013 complains "warning C4138: '*/' found outside of comment" about the code CallInst */*CI*/ but compiles OK. clang-formatting these lines adds an extra space and makes Visual C++ satisfied. llvm-svn: 232630
* Change test to accept an additional critical edge split.Daniel Jasper2015-03-181-2/+1
| | | | | | | | The two hot blocks are right next to each other and I verified that there is no performance regression by compressing/uncompressing some files with a minigzip built with the different options. llvm-svn: 232629
* [ARM] Align stack objects passed to memory intrinsicsJohn Brawn2015-03-186-21/+337
| | | | | | | | | | | | Memcpy, and other memory intrinsics, typically tries to use LDM/STM if the source and target addresses are 4-byte aligned. In CodeGenPrepare look for calls to memory intrinsics and, if the object is on the stack, 4-byte align it if it's large enough that we expect that memcpy would want to use LDM/STM to copy it. Differential Revision: http://reviews.llvm.org/D7908 llvm-svn: 232627
* Add missing newline to end of test file.John Brawn2015-03-181-1/+1
| | | | llvm-svn: 232626
* Remove many superfluous SmallString::str() calls.Yaron Keren2015-03-189-22/+22
| | | | | | | | | | | | | | | Now that SmallString is a first-class citizen, most SmallString::str() calls are not required. This patch removes a whole bunch of them, yet there are lots more. There are two use cases where str() is really needed: 1) To use one of StringRef member functions which is not available in SmallString. 2) To convert to std::string, as StringRef implicitly converts while SmallString do not. We may wish to change this, but it may introduce ambiguity. llvm-svn: 232622
* [mips] Add itineraries for ext and ins instructions.Kai Nacke2015-03-182-2/+6
| | | | | | | | | | | Currently, there are no itineraries defined for ext and ins instructions. This patch adds these itineraries and uses them in the instruction definitions. Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D7209 llvm-svn: 232613
* Split comma-separated \param(s). [-Wdocumentation]NAKAMURA Takumi2015-03-181-1/+2
| | | | llvm-svn: 232584
* [bpf] fix buildAlexei Starovoitov2015-03-181-1/+1
| | | | | | | | fix BPF backend build broken by r232429 Patch by Brenden Blanco llvm-svn: 232581
* Add testcases for BEXTR.Josh Magee2015-03-181-0/+30
| | | | | | These BEXTR cases are a check for the 64-bit load form and two negative cases where the bitrange is non-contiguous. From a private patch equivalent to r189742/PR17028. llvm-svn: 232580
* Missed testcase for r232577Krzysztof Parzyszek2015-03-181-0/+160
| | | | llvm-svn: 232578
* Generate bit manipulation instructions on HexagonKrzysztof Parzyszek2015-03-181-0/+149
| | | | llvm-svn: 232577
* [SCEV] Make isImpliedCond smarter.Sanjoy Das2015-03-183-0/+83
| | | | | | | | | | | | | | | | | | Summary: This change teaches isImpliedCond to infer things like "X sgt 0" => "X - 1 sgt -1". The `ConstantRange` class has the logic to do the heavy lifting, this change simply gets ScalarEvolution to exploit that when reasonable. Depends on D8345 Reviewers: atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8346 llvm-svn: 232576
* [ConstantRange] Split makeICmpRegion in two.Sanjoy Das2015-03-186-20/+96
| | | | | | | | | | | | | | | | | | | | Summary: This change splits `makeICmpRegion` into `makeAllowedICmpRegion` and `makeSatisfyingICmpRegion` with slightly different contracts. The first one is useful for determining what values some expression //may// take, given that a certain `icmp` evaluates to true. The second one is useful for determining what values are guaranteed to //satisfy// a given `icmp`. Reviewers: nlewycky Reviewed By: nlewycky Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8345 llvm-svn: 232575
* DAGCombiner: fold (xor (shl 1, x), -1) -> (rotl ~1, x)David Majnemer2015-03-182-0/+38
| | | | | | | | | | Targets which provide a rotate make it possible to replace a sequence of (XOR (SHL 1, x), -1) with (ROTL ~1, x). This saves an instruction on architectures like X86 and POWER(64). Differential Revision: http://reviews.llvm.org/D8350 llvm-svn: 232572
* COFF: Let globals with private linkage reside in their own sectionDavid Majnemer2015-03-1710-13/+56
| | | | | | | | | | COFF COMDATs (for selection kinds other than 'select any') require at least one non-section symbol in the symbol table. Satisfy this by morally enhancing the linkage from private to internal. Differential Revision: http://reviews.llvm.org/D8394 llvm-svn: 232570
* Remove unneeded selection functions from HexagonISelDAGToDAGKrzysztof Parzyszek2015-03-171-189/+0
| | | | | | | - SelectSelect, and - SelectTruncate llvm-svn: 232569
* docs: Update LangRef and SourceLevelDebuggingDuncan P. N. Exon Smith2015-03-172-672/+210
| | | | | | | | | | | | | | Cleanup some bitrot in SourceLevelDebugging.rst. - Pull the still-relevant details about individual descriptors into LangRef.rst. Cut a lot of it to avoid over-describing the fields, as the C++ classes and assembly format are mostly self-describing now. If there's anything specific that I shouldn't have cut, let me know and I'll add it back. - Rewrite the remaining sections to refer to the new debug info hierarchy in LangRef.rst. llvm-svn: 232566
* Fix bug while building FP16 constant vectors for AArch64Pirama Arumuga Nainar2015-03-172-2/+13
| | | | | | | | | | | | | | Summary: Building FP16 constant vectors caused the FP16 data to be bitcast to i64. This patch creates a BITCAST node with the correct value, and adds a test to verify correct handling. Reviewers: mcrosier Reviewed By: mcrosier Subscribers: mcrosier, jmolloy, ab, srhines, llvm-commits, rengolin, aemerson Differential Revision: http://reviews.llvm.org/D8369 llvm-svn: 232562
* Appease AArch64ISelLowering.cpp miscompiled by g++-4.7.2.NAKAMURA Takumi2015-03-171-0/+6
| | | | | | I will revert this when 4.7.3 is ready. llvm-svn: 232561
* Add the option -no-symbolic-operands to llvm-objdump used with -macho andKevin Enderby2015-03-172-3/+16
| | | | | | -disassemble to not symbolic operands when disassembling. llvm-svn: 232558
* XformToShuffleWithZero - Added clearer early outs and general tidy up. NFCISimon Pilgrim2015-03-171-31/+38
| | | | llvm-svn: 232557
* Selection DAG preprocessing on HexagonKrzysztof Parzyszek2015-03-171-2/+52
| | | | | | Simplify: (or (select c x 0) z) -> (select c (or x z) z) (or (select c 0 y) z) -> (select c z (or y z)) llvm-svn: 232553
* Remove StringRef->std::string->StringRef conversions.Yaron Keren2015-03-171-3/+3
| | | | | | | | As StringInit::get() accepts StringRef there is no need to construct a std::string out of the StringRef input and then construct a new StringRef from the std::string. llvm-svn: 232551
* DebugInfo: Drop fake DW_TAG_expressionDuncan P. N. Exon Smith2015-03-174-7/+3
| | | | | | | | | | | | | Break MDExpression off of DebugNode (inherit directly from `MDNode`) and drop the fake `DW_TAG_expression` tag in the process. AFAICT, there's no real functionality change here. The tag was originally used by `DIDescriptor::isExpression()` to discriminate between `MDNode`s, but in the new hierarchy we don't need that. Fixes PR22780. llvm-svn: 232550
* Emit the offset directly instead of creating a dummy expression.Rafael Espindola2015-03-172-26/+6
| | | | | | | | We were creating an expression of the form (S+C)-S which is just C. Patch by Frédéric Riss. I just added the testcase. llvm-svn: 232549
* Add the option, -no-leading-addr llvm-objdump used with -macho andKevin Enderby2015-03-173-20/+57
| | | | | | -disassemble or -section to not print the leading addresses on each line. llvm-svn: 232547
* [docs] Fix some malformed links.Sean Silva2015-03-172-2/+2
| | | | | | Patch by Stanislav Manilov! llvm-svn: 232546
* Revert "COFF: Let globals with private linkage reside in their own section"David Majnemer2015-03-176-42/+3
| | | | | | This reverts commit r232539. This was committed accidently. llvm-svn: 232543
* Internalize BitcodeReader. Not used outside of BitcodeReader.cpp.Benjamin Kramer2015-03-172-385/+342
| | | | | | NFC. llvm-svn: 232542
* Revert "Address review comments"David Majnemer2015-03-173-12/+13
| | | | | | This reverts commit r232540. This was committed accidently. llvm-svn: 232541
* Address review commentsDavid Majnemer2015-03-173-13/+12
| | | | llvm-svn: 232540
* COFF: Let globals with private linkage reside in their own sectionDavid Majnemer2015-03-176-3/+42
| | | | | | | | | | | | | | | Summary: COFF COMDATs (for selection kinds other than 'select any') require at least one non-section symbol in the symbol table. Satisfy this by morally enhancing the linkage from private to internal. Reviewers: rafael Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8374 llvm-svn: 232539
* Try to fix a test broken by one of my previous commits.Michael Zolotukhin2015-03-171-0/+3
| | | | llvm-svn: 232536
* Centralize the handling of unique ids for temporary labels.Rafael Espindola2015-03-1714-87/+64
| | | | | | | | | | | | | | | | Before this patch code wanting to create temporary labels for a given entity (function, cu, exception range, etc) had to keep its own counter to have stable symbol names. createTempSymbol would still add a suffix to make sure a new symbol was always returned, but it kept a single counter. Because of that, if we were to use just createTempSymbol("cu_begin"), the label could change from cu_begin42 to cu_begin43 because some other code started using temporary labels. Simplify this by just keeping one counter per prefix and removing the various specialized counters. llvm-svn: 232535
* Internalize llvm::AssemblyWriter. It's not used outside of AsmWriter.cpp.Benjamin Kramer2015-03-172-136/+86
| | | | | | | This is an artifact of an implementation detail of DebugIR that has been long refactored away. NFC. llvm-svn: 232532
* TLI: Add addVectorizableFunctionsFromVecLib.Michael Zolotukhin2015-03-173-0/+232
| | | | | | | | Also, add several entries to vectorizable functions table, and corresponding tests. The table isn't complete, it'll be populated later. Review: http://reviews.llvm.org/D8131 llvm-svn: 232531
* LoopVectorize: teach loop vectorizer to vectorize calls.Michael Zolotukhin2015-03-172-35/+164
| | | | | | | The tests would be committed in a commit for http://reviews.llvm.org/D8131 Review: http://reviews.llvm.org/D8095 llvm-svn: 232530
* TTI: Honour cost model for estimating cost of vector-intrinsic and calls.Michael Zolotukhin2015-03-173-28/+46
| | | | | Review: http://reviews.llvm.org/D8096 llvm-svn: 232528
* Add assertion to detect invalid registers in the PowerPC MC instruction ↵Samuel Antao2015-03-171-0/+3
| | | | | | | | lowering. We have observed that noreg was being generated due to a bug in FastIsel and was not being detected during emission. It happens that in the Asm emission there is an assertion that detects this in getRegisterName() from the tbl-generated file PPCGenAsmWriter.inc. However, when emitting an Obj file, invalid registers can be emitted given that no check are made in getBinaryCodeFromInstr() from PPCGenMCCodeEmitter.inc. In order to cover all cases this adds an assertion for reg operands in LowerPPCMachineInstrToMCInst. llvm-svn: 232525
* TTI: Add getCallInstrCost.Michael Zolotukhin2015-03-174-0/+34
| | | | | Review: http://reviews.llvm.org/D8094 llvm-svn: 232524
* TLI: Add interface for querying whether a function is vectorizable.Michael Zolotukhin2015-03-172-0/+125
| | | | | Review: http://reviews.llvm.org/D8093 llvm-svn: 232523
* LoopVectorizer: Add TargetTransformInfo.Michael Zolotukhin2015-03-171-9/+12
| | | | | Review: http://reviews.llvm.org/D8092 llvm-svn: 232522
* [asan] remove redundant ifndefs. NFCKostya Serebryany2015-03-171-9/+5
| | | | llvm-svn: 232521
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