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* Strip llvm.dbg.lv also.Devang Patel2010-05-201-0/+6
| | | | llvm-svn: 104236
* Rename a variable to avoid shadowing.Dan Gohman2010-05-201-2/+3
| | | | llvm-svn: 104234
* Split DbgVariable. Eventually, variable info will be communicated through ↵Devang Patel2010-05-202-94/+111
| | | | | | frame index, or DBG_VALUE instruction, or collection of DBG_VALUE instructions. Plus each DbgVariable may not need a label. llvm-svn: 104233
* Minor code simplification.Dan Gohman2010-05-201-4/+4
| | | | llvm-svn: 104232
* Fix assembly parsing and encoding of the pushf and popf family ofDan Gohman2010-05-207-10/+60
| | | | | | instructions. llvm-svn: 104231
* Set neverHasSideEffects on 64-bit pushf and popf, for consistency withDan Gohman2010-05-201-2/+2
| | | | | | 16-bit and 32-bit pushf and popf. llvm-svn: 104228
* Move the code for deleting BaseRegs and LSRUses into helper functions,Dan Gohman2010-05-201-5/+22
| | | | | | | and fix a bug that valgrind noticed where the code would std::swap an element with itself. llvm-svn: 104225
* Reduce string trashing.Benjamin Kramer2010-05-201-2/+2
| | | | llvm-svn: 104223
* Add a hybrid bottom up scheduler that reduce register usage while avoidingEvan Cheng2010-05-208-31/+162
| | | | | | | | | pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot of long latency instructions so a strict register pressure reduction scheduler does not work well. Early experiments show this speeds up some NEON loops by over 30%. llvm-svn: 104216
* Fix typo in comment.Nick Lewycky2010-05-201-2/+2
| | | | llvm-svn: 104209
* Define the x86 pause instruction.Dan Gohman2010-05-203-0/+13
| | | | llvm-svn: 104204
* Fix the sfence instruction to use MRM_F8 instead of MRM7r, since itDan Gohman2010-05-202-1/+5
| | | | | | | doesn't have a register operand. Also, use I instead of PSI, for consistency with mfence and lfence. llvm-svn: 104203
* Fix build by actually declaring the variable.Eric Christopher2010-05-201-0/+4
| | | | llvm-svn: 104201
* Partial code for emitting thread local bss data.Eric Christopher2010-05-204-0/+10
| | | | llvm-svn: 104197
* Match "4" or "8" depending upon if it's 32- or 64-bit.Bill Wendling2010-05-201-2/+2
| | | | llvm-svn: 104196
* Once more, with feeling.Eric Christopher2010-05-201-0/+1
| | | | llvm-svn: 104190
* lit: Add another place to look for bash.Daniel Dunbar2010-05-191-1/+1
| | | | llvm-svn: 104189
* Teach LSR how to cope better with unrolled loops on targets whereDan Gohman2010-05-192-3/+577
| | | | | | | | the addressing modes don't make this trivially easy. This allows it to avoid falling into the less precise heuristics in more cases. llvm-svn: 104186
* Optimize away insertelement of an undef value. This shows up inBob Wilson2010-05-191-0/+4
| | | | | | | test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code because the coalescer cleans it up. Radar 7998853. llvm-svn: 104185
* fix rdar://7986634 - match instruction opcodes case insensitively.Chris Lattner2010-05-192-1/+11
| | | | llvm-svn: 104183
* Testcase for r104181.Bill Wendling2010-05-191-0/+33
| | | | llvm-svn: 104182
* Enable preserving debug information through post-RA schedulingJim Grosbach2010-05-191-1/+1
| | | | llvm-svn: 104175
* Fix the post-RA instruction scheduler to handle instructions referenced byJim Grosbach2010-05-192-21/+8
| | | | | | more than one dbg_value instruction. rdar://7759363 llvm-svn: 104174
* Code clean up.Evan Cheng2010-05-191-7/+7
| | | | llvm-svn: 104173
* Revert r104165.Devang Patel2010-05-192-5/+13
| | | | llvm-svn: 104172
* Add support for partial redefs to the fast register allocator.Jakob Stoklund Olesen2010-05-191-20/+18
| | | | | | | | | | A partial redef now triggers a reload if required. Also don't add <imp-def,dead> operands for physical superregisters. Kill flags are still treated as full register kills, and <imp-use,kill> operands are added for physical superregisters as before. llvm-svn: 104167
* There is no need to maintain InsnsBeginScopeSet separately. Devang Patel2010-05-192-13/+5
| | | | llvm-svn: 104165
* A more combo tls testcase.Eric Christopher2010-05-191-0/+232
| | | | llvm-svn: 104163
* Add MachineInstr::readsVirtualRegister() in preparation for proper handling ofJakob Stoklund Olesen2010-05-192-1/+31
| | | | | | | | | | | | | | | | | | partial redefines. We are going to treat a partial redefine of a virtual register as a read-modify-write: %reg1024:6 = OP Unless the register is fully clobbered: %reg1024:6 = OP, %reg1024<imp-def> MachineInstr::readsVirtualRegister() knows the difference. The first case is a read, the second isn't. llvm-svn: 104149
* Few more simple tls testcases.Eric Christopher2010-05-193-0/+279
| | | | llvm-svn: 104148
* Code refactoring: pull SchedPreference enum from TargetLowering.h to ↵Evan Cheng2010-05-1910-18/+20
| | | | | | TargetMachine.h and put it in its own namespace. llvm-svn: 104147
* TwoAddressInstructionPass doesn't really know how to merge live intervals whenJakob Stoklund Olesen2010-05-192-1/+23
| | | | | | | | lowering REG_SEQUENCE instructions. Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes. llvm-svn: 104146
* llvmc: report an error if a child process segfaults.Mikhail Glushenkov2010-05-191-1/+14
| | | | llvm-svn: 104145
* Attempt to run this test on x86 only.Eric Christopher2010-05-191-0/+1
| | | | llvm-svn: 104143
* Testcase to go with 104141.Bob Wilson2010-05-191-0/+14
| | | | llvm-svn: 104142
* When expanding a vector_shuffle, the element type may not be legal and mayBob Wilson2010-05-191-0/+2
| | | | | | | | need to be promoted. The BUILD_VECTOR and EXTRACT_VECTOR_ELT nodes generated here already allow the promoted type to be used without further changes, so just do the promotion. This fixes part of pr7167. llvm-svn: 104141
* MC/X86: Add missing entry for TAILJMP_1 to getRelaxedOpcode().Daniel Dunbar2010-05-191-0/+1
| | | | llvm-svn: 104122
* MC/X86: Lower TAILCALLd[64] to JMP_1, to allow relaxation and to avoid sameDaniel Dunbar2010-05-192-0/+17
| | | | | | | prefix byte problem as in r104062. - As a total hack to keep the TAILCALL markers in the output, which some tests depend on, this invents a new TAILJMP_1 instruction. llvm-svn: 104120
* MC/X86: Strip spurious operands from TAILJMPr64 as we do for CALL64r andDaniel Dunbar2010-05-191-3/+5
| | | | | | CALL64pcrel32, for the same reason. llvm-svn: 104116
* t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to ↵Evan Cheng2010-05-193-6/+41
| | | | | | hoist more loads during machine LICM. llvm-svn: 104115
* Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable.Evan Cheng2010-05-191-12/+4
| | | | llvm-svn: 104114
* Update autoconf/automake versions in the documentation to match the versions ↵Tobias Grosser2010-05-191-2/+2
| | | | | | used in Autogen.sh llvm-svn: 104113
* MC/X86: Lower MOV{8,16,32,64}{rm,mr} to fixed-register forms, as appropriate.Daniel Dunbar2010-05-191-9/+50
| | | | llvm-svn: 104112
* Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These ↵Evan Cheng2010-05-195-35/+37
| | | | | | do not have other un-modeled side effects. llvm-svn: 104111
* Target instruction selection should copy memoperands.Evan Cheng2010-05-191-3/+11
| | | | llvm-svn: 104110
* MC/X86: Strip spurious operands from CALL64r as we do for CALL64pcrel32, toDaniel Dunbar2010-05-191-6/+8
| | | | | | avoid same prefix byte problem as in r104062. llvm-svn: 104108
* Mark a few more pattern-less instructions with neverHasSideEffects. This is ↵Evan Cheng2010-05-193-0/+12
| | | | | | especially important on instructions like t2LEApcreal which are prime candidate for machine LICM. llvm-svn: 104102
* Add a comment explaining why this code uses Append mode.Dan Gohman2010-05-191-0/+4
| | | | llvm-svn: 104095
* Intrinsics which do a vector compare (results are all zero or all ones) are ↵Evan Cheng2010-05-192-6/+88
| | | | | | | | | | modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction. The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that. Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010. llvm-svn: 104094
* Factor out the code for picking integer arithmetic with immediateDan Gohman2010-05-191-15/+32
| | | | | | | opcodes into a helper function. This fixes a few places in the code which were not properly selecting the 8-bit-immediate opcodes. llvm-svn: 104091
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