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* This break is bogus and I have no idea why it was there. Basically it preventsChris Lattner2005-10-031-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | memoizing code when IV's are used by phinodes outside of loops. In a simple example, we were getting this code before (note that r6 and r7 are isomorphic IV's): li r6, 0 or r7, r6, r6 LBB_test_3: ; no_exit lwz r2, 0(r3) cmpw cr0, r2, r5 or r2, r7, r7 beq cr0, LBB_test_5 ; loopexit LBB_test_4: ; endif addi r2, r7, 1 addi r7, r7, 1 addi r3, r3, 4 addi r6, r6, 1 cmpw cr0, r6, r4 blt cr0, LBB_test_3 ; no_exit Now we get: li r6, 0 LBB_test_3: ; no_exit or r2, r6, r6 lwz r6, 0(r3) cmpw cr0, r6, r5 beq cr0, LBB_test_6 ; loopexit LBB_test_4: ; endif addi r3, r3, 4 addi r6, r2, 1 cmpw cr0, r6, r4 blt cr0, LBB_test_3 ; no_exit this was noticed in em3d. llvm-svn: 23602
* when checking if we should move a split edge block outside of a loop,Chris Lattner2005-10-031-7/+6
| | | | | | | | check the presplit pred, not the post-split pred. This was causing us to make the wrong decision in some cases, leaving the critical edge block in the loop. llvm-svn: 23601
* This member can be const tooChris Lattner2005-10-031-1/+1
| | | | llvm-svn: 23600
* put the right labels on the dataChris Lattner2005-10-021-96/+96
| | | | llvm-svn: 23599
* Fix a problem where the legalizer would run out of stack space on extremelyChris Lattner2005-10-021-9/+36
| | | | | | | large basic blocks because it was purely recursive. This switches it to an iterative/recursive hybrid. llvm-svn: 23596
* silence a bogus warningChris Lattner2005-10-021-1/+1
| | | | llvm-svn: 23595
* silence some warningsChris Lattner2005-10-021-3/+2
| | | | llvm-svn: 23594
* silence a warningChris Lattner2005-10-021-1/+1
| | | | llvm-svn: 23593
* add patterns for float binops and fma opsChris Lattner2005-10-021-8/+12
| | | | llvm-svn: 23592
* Sort the cpu and features table, so that the alpha backend doesn't fail EVERYChris Lattner2005-10-021-2/+2
| | | | | | compile with an assertion that the tables are not sorted! llvm-svn: 23591
* Add assertions to the trivial scheduler to check that the value types matchChris Lattner2005-10-021-0/+21
| | | | | | up between defs and uses. llvm-svn: 23590
* another solution to the fsel issue. Instead of having 4 variants, just forceChris Lattner2005-10-023-32/+25
| | | | | | | the comparison to be 64-bits. This is fine because extensions from float to double are free. llvm-svn: 23589
* fsel can take a different FP type for the comparison and for the result. As ↵Chris Lattner2005-10-023-22/+37
| | | | | | | | such split the FSEL family into 4 things instead of just two. llvm-svn: 23588
* fix an f32/f64 type mismatchChris Lattner2005-10-021-2/+6
| | | | llvm-svn: 23587
* Codegen CopyFromReg using the regclass that matches the valuetype of theChris Lattner2005-10-021-9/+11
| | | | | | destination vreg. llvm-svn: 23586
* Adjust to change in ctorChris Lattner2005-10-021-5/+5
| | | | llvm-svn: 23585
* Emit the value type for each register class.Chris Lattner2005-10-021-3/+4
| | | | llvm-svn: 23584
* Expose the actual valuetype of each register classChris Lattner2005-10-021-2/+8
| | | | llvm-svn: 23583
* Minor tweak to the branch selector. When emitting a two-way branch, and ifChris Lattner2005-10-011-6/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | we're in a single-mbb loop, make sure to emit the backwards branch as the conditional branch instead of the uncond branch. For example, emit this: LBBl29_z__44: stw r9, 0(r15) stw r9, 4(r15) stw r9, 8(r15) stw r9, 12(r15) addi r15, r15, 16 addi r8, r8, 1 cmpw cr0, r8, r28 ble cr0, LBBl29_z__44 b LBBl29_z__48 *** NOT PART OF LOOP Instead of: LBBl29_z__44: stw r9, 0(r15) stw r9, 4(r15) stw r9, 8(r15) stw r9, 12(r15) addi r15, r15, 16 addi r8, r8, 1 cmpw cr0, r8, r28 bgt cr0, LBBl29_z__48 *** PART OF LOOP! b LBBl29_z__44 The former sequence has one fewer dispatch group for the loop body. llvm-svn: 23582
* like the comment says, enable thisChris Lattner2005-10-011-3/+1
| | | | llvm-svn: 23581
* Add some very paranoid checking for operand/result reg class matchupChris Lattner2005-10-011-3/+20
| | | | | | | For instructions that define multiple results, use the right regclass to define the result, not always the rc of result #0 llvm-svn: 23580
* Fix VC++ warnings.Jeff Cohen2005-10-012-5/+4
| | | | llvm-svn: 23579
* fix typoChris Lattner2005-10-011-1/+1
| | | | llvm-svn: 23578
* Modify the ppc backend to use two register classes for FP: F8RC and F4RC.Chris Lattner2005-10-019-152/+253
| | | | | | | These are used to represent float and double values, and the two regclasses contain the same physical registers. llvm-svn: 23577
* Annotate nodes with their addresses if a graph requests it.Chris Lattner2005-10-011-2/+13
| | | | | | | This is Jim's feature implemented so that graphs could 'opt-in' and get this behavior. This is currently used by selection dags. llvm-svn: 23576
* add a methodChris Lattner2005-10-012-0/+11
| | | | llvm-svn: 23575
* typoJim Laskey2005-10-011-1/+1
| | | | llvm-svn: 23574
* 1. Simplify the gathering of node groups.Jim Laskey2005-10-011-54/+22
| | | | | | 2. Printing node groups when displaying nodes. llvm-svn: 23573
* Should be using flag and not chain.Jim Laskey2005-09-301-1/+1
| | | | llvm-svn: 23572
* Remove some now-dead code.Nate Begeman2005-09-301-15/+4
| | | | llvm-svn: 23571
* more specific tests of subtarget stuffAndrew Lenharth2005-09-302-2/+11
| | | | llvm-svn: 23570
* subtarget support for CIX and FIX extentions (the only 2 I care about right now)Andrew Lenharth2005-09-301-2/+35
| | | | llvm-svn: 23569
* Reverting change moving to selection dag graph.Jim Laskey2005-09-301-1/+1
| | | | llvm-svn: 23568
* Added allnodes_size for scheduling support.Jim Laskey2005-09-301-0/+1
| | | | llvm-svn: 23567
* 1. Made things node-centric (from operand).Jim Laskey2005-09-301-244/+609
| | | | | | | | 2. Added node groups to handle flagged nodes. 3. Started weaning simple scheduling off existing emitter. llvm-svn: 23566
* Add the node name (thus the address) to node label.Jim Laskey2005-09-301-1/+1
| | | | llvm-svn: 23565
* Rename MRegisterDesc -> TargetRegisterDesc for consistencyChris Lattner2005-09-304-14/+16
| | | | llvm-svn: 23564
* Update the discussion of TargetRegisterDescChris Lattner2005-09-301-3/+3
| | | | llvm-svn: 23563
* remove some more initializersChris Lattner2005-09-301-1/+1
| | | | llvm-svn: 23562
* trim down the target info structs now that we have a preferred spill ↵Chris Lattner2005-09-301-104/+104
| | | | | | | | register class for each callee save register Why is V9 maintaining these tables manually? ugh! llvm-svn: 23561
* trim down the target info structs now that we have a preferred spill ↵Chris Lattner2005-09-302-31/+2
| | | | | | register class for each callee save register llvm-svn: 23560
* now that we have a reg class to spill with, get this info from the regclassChris Lattner2005-09-301-4/+3
| | | | llvm-svn: 23559
* constant fold these callsChris Lattner2005-09-301-2/+2
| | | | llvm-svn: 23558
* simplify this code using the new regclass info passed inChris Lattner2005-09-301-29/+45
| | | | llvm-svn: 23557
* Now that we have getCalleeSaveRegClasses() info, use it to pass the registerChris Lattner2005-09-301-8/+11
| | | | | | class into the spill/reload methods. Targets can now rely on that argument. llvm-svn: 23556
* expose a new virtual methodChris Lattner2005-09-301-0/+7
| | | | llvm-svn: 23555
* stub out a virtual methodChris Lattner2005-09-301-0/+4
| | | | llvm-svn: 23554
* Compute a preferred spill register class for each callee-save registerChris Lattner2005-09-301-1/+24
| | | | llvm-svn: 23553
* CR registers are not used by this "target"Chris Lattner2005-09-302-8/+1
| | | | llvm-svn: 23552
* these registers don't belong to any register classes, so don't mark themChris Lattner2005-09-301-11/+21
| | | | | | as callee save. They can never be generated by the compiler. llvm-svn: 23551
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