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* [LV] Account for predicated stores in instruction costsMatthew Simpson2016-10-132-1/+45
| | | | | | | This patch ensures that we scale the estimated cost of predicated stores by block probability. This is a follow-on patch for r284123. llvm-svn: 284126
* [x86] add negate-i1 run for 32-bit targetSanjay Patel2016-10-131-51/+112
| | | | llvm-svn: 284124
* [LV] Avoid rounding errors for predicated instruction costsMatthew Simpson2016-10-132-26/+82
| | | | | | | | | | | | This patch modifies the cost calculation of predicated instructions (div and rem) to avoid the accumulation of rounding errors due to multiple truncating integer divisions. The calculation for predicated stores will be addressed in a follow-on patch since we currently don't scale the cost of predicated stores by block probability. Differential Revision: https://reviews.llvm.org/D25333 llvm-svn: 284123
* [DAGCombiner] Add vector support to (mul (shl X, Y), Z) -> (shl (mul X, Z), ↵Simon Pilgrim2016-10-132-10/+8
| | | | | | Y) style combines llvm-svn: 284122
* AMDGPU: Assume spilling will occur at -O0Matt Arsenault2016-10-133-33/+70
| | | | | | | | Because everything live is spilled at the end of a block by fast regalloc, assume this will happen and avoid the copies of the resource descriptor. llvm-svn: 284119
* Copy+pasts typo in comment describing combine testSimon Pilgrim2016-10-131-1/+1
| | | | | | Repeated the "fold (mul x, 0) -> 0" instead of "fold (mul x, 1) -> x" llvm-svn: 284118
* [DAGCombiner] Add vector support to C2-(A+C1) -> (C2-C1)-A foldingSimon Pilgrim2016-10-132-9/+7
| | | | llvm-svn: 284117
* AMDGPU: Fix truncate to bool warningsMatt Arsenault2016-10-131-5/+5
| | | | llvm-svn: 284116
* [mips] Add IAS support for dvp, evpSimon Dardis2016-10-1314-4/+88
| | | | | | | | | | | | | These instructions were only defined for microMIPSR6 previously. Add definitions for MIPSR6, correct definitions for microMIPSR6, flag these instructions as having unmodelled side effects (they disable/enable virtual processors) and add missing disassember tests for microMIPSR6. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24291 llvm-svn: 284115
* [DAGCombiner] Add vector support to (sub -1, x) -> (xor x, -1) canonicalizationSimon Pilgrim2016-10-132-4/+14
| | | | | | Improves commutation potential llvm-svn: 284113
* [X86] Basic additions to support RegCall Calling Convention.Oren Ben Simhon2016-10-1310-0/+1044
| | | | | | | | | | The Register Calling Convention (RegCall) was introduced by Intel to optimize parameter transfer on function call. This calling convention ensures that as many values as possible are passed or returned in registers. This commit presents the basic additions to LLVM CodeGen in order to support RegCall in X86. Differential Revision: http://reviews.llvm.org/D25022 llvm-svn: 284108
* Silence unused warning in non-assert builds.Daniel Jasper2016-10-131-3/+3
| | | | llvm-svn: 284107
* [AVX-512] Fix v16i32 zero extending shuffle test case so it's really zero ↵Craig Topper2016-10-131-7/+4
| | | | | | extend. llvm-svn: 284106
* [AVX-512] Teach shuffle lowering to recognize 512-bit zero extends.Craig Topper2016-10-133-21/+32
| | | | llvm-svn: 284105
* [AVX-512] Add tests for basic 512-bit zero extending shuffle patterns. Code ↵Craig Topper2016-10-133-0/+121
| | | | | | will be improved in a future commit. llvm-svn: 284104
* Remove a FIXME that I forgot about. NFC.Diana Picus2016-10-131-2/+0
| | | | | | Sorry about the noise. llvm-svn: 284103
* [X86] Simplify the lowering code for extracting and inserting subvectors.Craig Topper2016-10-131-24/+21
| | | | | | | We don't need to check if AVX is enabled. It's implied by the operation action being set to Custom. We don't need to check both the input and output type widths. We only need to check the type that's being inserted or extracted. The other type is known to be a legal type and we can assume its a different width. llvm-svn: 284102
* Memory-SSA: strengthen defClobbersUseOrDef interfaceSebastian Pop2016-10-131-19/+15
| | | | | | | As Danny pointed out, defClobbersUseOrDef should use MemoryLocOrCall to make sure fences are properly handled. llvm-svn: 284099
* commit back "GVN-hoist: fix store past load dependence analysis (PR30216, ↵Sebastian Pop2016-10-135-90/+195
| | | | | | | | | | PR30499)" This is with an extra change to avoid calling MemoryLocation::get() on a call instruction. Differential Revision: https://reviews.llvm.org/D25542 llvm-svn: 284098
* [AArch64][RegisterBankInfo] Provide alternative mappings for 64-bit loadQuentin Colombet2016-10-132-1/+89
| | | | | | | | This allows RegBankSelect in greedy mode to get rid some of the cross register bank copies when loads are involved in the chain of computation. llvm-svn: 284097
* Correct PrivateLinkage for COFFReid Kleckner2016-10-135-13/+13
| | | | | | | | | | | | | - Use storage class C_STAT for 'PrivateLinkage' The storage class for PrivateLinkage should equal to the Internal Linkage. - Set 'PrivateGlobalPrefix' from "L" to ".L" for MM_WinCOFF (includes x86_64) MM_WinCOFF has empty GlobalPrefix '\0' so PrivateGlobalPrefix "L" may conflict to the normal symbol name starting with 'L'. Based on a patch by Han Sangjin! Manually updated test cases. llvm-svn: 284096
* [AArch64][RegisterBankInfo] Provide alternative mappings for G_BITCASTs.Quentin Colombet2016-10-132-12/+53
| | | | | | | Thanks to this patch, RegBankSelect is able to get rid of some register bank copies as demonstrated in the test case. llvm-svn: 284094
* Revert "GVN-hoist: fix store past load dependence analysis (PR30216, PR30499)"Reid Kleckner2016-10-135-190/+90
| | | | | | | | | | | This CL didn't actually address the test case in PR30499, and clang still crashes. Also revert dependent change "Memory-SSA cleanup of clobbers interface, NFC" Reverts r283965 and r283967. llvm-svn: 284093
* [AArch64][RegisterBankInfo] Describe cross regbank copies statically.Quentin Colombet2016-10-132-2/+68
| | | | | | NFC. llvm-svn: 284091
* [AArch64][RegisterBankInfo] Use static mapping for same bank G_BITCAST.Quentin Colombet2016-10-132-0/+200
| | | | | | NFC. llvm-svn: 284090
* [AArch64][MachineLegalizer] Mark more G_BITCAST as legal.Quentin Colombet2016-10-132-1/+11
| | | | | | | Basically any vector types that fits in a 32-bit register is also valid as far as copies are concerned. llvm-svn: 284089
* [AArch64][RegisterBankInfo] Bump the cost of vector loads.Quentin Colombet2016-10-131-0/+10
| | | | | | | This does not change anything yet, because we do not offer any alternative mapping. llvm-svn: 284088
* [AArch64][RegisterBankInfo] Use a proper cost for cross regbank G_BITCASTs.Quentin Colombet2016-10-131-2/+11
| | | | | | | This does not change anything yet, because we do not offer any alternative mapping. llvm-svn: 284087
* [AArch64][RegisterBankInfo] Provide more realistic copy costs.Quentin Colombet2016-10-131-1/+10
| | | | llvm-svn: 284086
* fix function label name in addressofreturnaddress testAlbert Gutowski2016-10-121-1/+1
| | | | llvm-svn: 284085
* [GitHubMove Doc] Properly nest a subsection in the proposalMehdi Amini2016-10-121-1/+1
| | | | llvm-svn: 284082
* fix title underline lengthAlbert Gutowski2016-10-121-1/+1
| | | | llvm-svn: 284078
* Moving to GitHub - Unified ProposalMehdi Amini2016-10-123-275/+870
| | | | | | | | | | | | | | | This document describes the proposal to move to GitHub, and compare the two proposals through various workflow examples, presenting the current set of commands following by the ones involved in each of the two proposals. It is intended to supersede the previous "submodule proposal" document entirely, and drive the discussion at the BoF during the next Dev Meeting. Differential Revision: https://reviews.llvm.org/D24167 llvm-svn: 284077
* Handle lane masks in LivePhysRegs when adding live-insKrzysztof Parzyszek2016-10-123-5/+57
| | | | | | Differential Revision: https://reviews.llvm.org/D25533 llvm-svn: 284076
* GlobalISel: support G_TRUNC selection on AArch64.Tim Northover2016-10-122-0/+117
| | | | | | Ahmed's patch again. llvm-svn: 284075
* GlobalISel: support int <-> float conversions on AArch64.Tim Northover2016-10-122-1/+499
| | | | | | More of Ahmed's work. llvm-svn: 284074
* GlobalISel: select G_FCMP instructions on AArch64.Tim Northover2016-10-122-0/+157
| | | | | | Another of Ahmed's patches. llvm-svn: 284073
* GlobalISel: support selection of G_ICMP on AArch64.Tim Northover2016-10-122-0/+117
| | | | | | Patch from Ahmed Bougaca again. llvm-svn: 284072
* GlobalISel: select G_BRCOND instructions on AArch64.Tim Northover2016-10-122-0/+46
| | | | llvm-svn: 284071
* GlobalISel: mark G_BRCOND on s1 as legal.Tim Northover2016-10-122-5/+4
| | | | | | It's going to be a TBNZ (at -O0) anyway, so the high bits don't matter. llvm-svn: 284070
* [unittests] Delete even more copy constructors (NFC)Vedant Kumar2016-10-121-0/+10
| | | | llvm-svn: 284069
* [unittests] Delete some copy constructors (NFC)Vedant Kumar2016-10-121-0/+11
| | | | llvm-svn: 284066
* [unittest] Pass a reference instead of making a copy (NFC)Vedant Kumar2016-10-121-1/+1
| | | | llvm-svn: 284065
* [Coverage] Delete some copy constructors (NFC)Vedant Kumar2016-10-122-1/+12
| | | | llvm-svn: 284064
* [Coverage] Factor out logic to create FunctionRecords (NFC)Vedant Kumar2016-10-122-40/+50
| | | | llvm-svn: 284063
* Create llvm.addressofreturnaddress intrinsicAlbert Gutowski2016-10-1212-3/+89
| | | | | | | | | | | | Summary: We need a new LLVM intrinsic to implement MS _AddressOfReturnAddress builtin on 64-bit Windows. Reviewers: majnemer, rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25293 llvm-svn: 284061
* Update _MSC_VER equality checks for msdiaNNN.dllReid Kleckner2016-10-121-10/+6
| | | | | | | | | Use inequality instead of equality to defend against minor version increases in _MSC_VER. An _MSC_VER value of 1901 should still use msdia140.dll, as described in this blog post: https://blogs.msdn.microsoft.com/vcblog/2016/10/05/visual-c-compiler-version/ llvm-svn: 284058
* [lit] Fix test shtest-timeout.py for modern outputMichal Gorny2016-10-121-10/+9
| | | | | | | | | | Update the CHECK lines in the shtest-timeout.py lit test to account for the current output. The output has been changed in r271610 without adjusting the tests. Differential Revision: https://reviews.llvm.org/D25236 llvm-svn: 284057
* [lit] Fix FormatError on individual test timeoutMichal Gorny2016-10-121-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D25195 llvm-svn: 284056
* Reapply "[LoopUnroll] Use the upper bound of the loop trip count to fullly ↵Haicheng Wu2016-10-1210-51/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | unroll a loop" Reappy r284044 after revert in r284051. Krzysztof fixed the error in r284049. The original summary: This patch tries to fully unroll loops having break statement like this for (int i = 0; i < 8; i++) { if (a[i] == value) { found = true; break; } } GCC can fully unroll such loops, but currently LLVM cannot because LLVM only supports loops having exact constant trip counts. The upper bound of the trip count can be obtained from calling ScalarEvolution::getMaxBackedgeTakenCount(). Part of the patch is the refactoring work in SCEV to prevent duplicating code. The feature of using the upper bound is enabled under the same circumstance when runtime unrolling is enabled since both are used to unroll loops without knowing the exact constant trip count. llvm-svn: 284053
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