| Commit message (Collapse) | Author | Age | Files | Lines |
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Instead of annotating (most of) the StringRef API, we can just
annotate the type directly. This is less code and it will warn in more
cases.
llvm-svn: 284364
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existing support for vpermt2var.
llvm-svn: 284357
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Combining will be added in a future commit.
llvm-svn: 284356
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an insert_subvector into a subvector broadcast.
Differential Revision: https://reviews.llvm.org/D25650
llvm-svn: 284353
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Ideally these would actually check that the results are reasonable,
but given that we're looping over so many different kinds of path that
isn't really practical.
llvm-svn: 284350
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Simplify this a little bit since the result is never used. It can be
added back easily enough if that changes.
llvm-svn: 284348
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Update a function annotated with LLVM_ATTRIBUTE_UNUSED_RESULT to use
LLVM_NODISCARD instead.
llvm-svn: 284346
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Update functions annotated with LLVM_ATTRIBUTE_UNUSED_RESULT to use
LLVM_NODISCARD instead.
llvm-svn: 284345
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Update functions annotated with LLVM_ATTRIBUTE_UNUSED_RESULT to use
LLVM_NODISCARD instead.
llvm-svn: 284344
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Update functions annotated with LLVM_ATTRIBUTE_UNUSED_RESULT to use
LLVM_NODISCARD instead.
llvm-svn: 284343
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Instead of annotating (most of) the ArrayRef API, we can just annotate
the type directly. This is less code and it will warn in more cases.
llvm-svn: 284342
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fix TBAA violation in profiling of pointers.
llvm-svn: 284336
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other vpermi2var intrinsics.
llvm-svn: 284329
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llvm-svn: 284328
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HasVLX predicate. Similar for floating point.
llvm-svn: 284327
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llvm-svn: 284320
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SDNode to MachineMemOperand, and remove redundant getAtomic* member functions from SelectionDAG.
Differential Revision: https://reviews.llvm.org/D24577
llvm-svn: 284312
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In theory this could be generalized to move anything where
we prove the operands are available, but that would require
rewriting PRE. As NewGVN will hopefully come soon, and we're
trying to rewrite PRE in terms of NewGVN+MemorySSA, it's probably
not worth spending too much time on it. Fix provided by
Daniel Berlin!
llvm-svn: 284311
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computeKnownBits only returns the common bits of each vector element instead of only the elements that are actually used
llvm-svn: 284308
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llvm-svn: 284307
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llvm-svn: 284306
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llvm-svn: 284305
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to match the mnemonic which does not include a 'P'.
llvm-svn: 284304
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BasicBlock::size is O(insts), making this loop O(blocks*insts), which
can be really slow on generated code. getPrevNode already checks if
we're at the beginning of the block and returns nullptr if so, just use
that instead. No functionality change intended.
llvm-svn: 284303
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llvm-svn: 284301
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llvm-svn: 284299
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Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D25526
llvm-svn: 284298
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Instead of annotating (most of) the APInt API, we can just annotate
the type directly. This is less code and it will warn in more cases.
llvm-svn: 284297
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- Removed unused class members.
- Made class internal data private.
- Made class scoped data function scoped where it's possible.
- Replace naked new/delete with unique_ptr.
- Made resources guaranteed to be freed.
Differential Revision: https://reviews.llvm.org/D25464
llvm-svn: 284290
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The previous names were both misleading (the MachineLegalizer actually
contained the info tables) and inconsistent with the selector & translator (in
having a "Machine") prefix. This should make everything sensible again.
The only functional change is the name of a couple of command-line options.
llvm-svn: 284287
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This is essentially a more powerful version of our current
LLVM_ATTRIBUTE_UNUSED_RESULT, in that it can also be applied to types
and generate warnings whenever an object of that type is returned by
value and the value is discarded.
I'll replace uses of LLVM_ATTRIBUTE_UNUSED_RESULT and remove that
macro in follow up commits.
llvm-svn: 284286
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LLVM_ENABLE_THREADS=OFF
llvm-svn: 284283
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llvm-svn: 284281
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llvm-svn: 284280
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llvm-svn: 284279
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This is a patch to implement pr30640.
When a 64bit constant has the same hi/lo words, we can use rldimi to copy the low word into high word of the same register.
This optimization caused failure of test case bperm.ll because of not optimal heuristic in function SelectAndParts64. It chooses AND or ROTATE to extract bit groups from a register, and OR them together. This optimization lowers the cost of loading 64bit constant mask used in AND method, and causes different code sequence. But actually ROTATE method is better in this test case. The reason is in ROTATE method the final OR operation can be avoided since rldimi can insert the rotated bits into target register directly. So this patch also enhances SelectAndParts64 to prefer ROTATE method when the two methods have same cost and there are multiple bit groups need to be ORed together.
Differential Revision: https://reviews.llvm.org/D25521
llvm-svn: 284276
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https://github.com/google/fuzzer-test-suite
llvm-svn: 284275
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instructions). This is a reincarnation of the previously deleted -use_traces, but using a different approach for collecting traces. Still a toy, but at least it scales well. Also fix -merge in trace-pc-guard mode
llvm-svn: 284273
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Add missing attribute to the keyword set.
llvm-svn: 284270
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The attribute may be applied to a function. Highlight it as a keyword.
llvm-svn: 284269
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Eli noted this potential bug in the post-commit thread for:
https://reviews.llvm.org/rL284239
...but I'm not sure how to trigger it, so there's no test case yet.
llvm-svn: 284268
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Summary:
We are using this helper for our 24-bit arithmetic combines, so we are now able to eliminate multi-use operations that mask the high-bits of 24-bit inputs (e.g. and x, 0xffffff)
Reviewers: arsenm, nhaehnle
Subscribers: tony-tye, arsenm, kzhuravl, wdng, nhaehnle, llvm-commits, yaxunl
Differential Revision: https://reviews.llvm.org/D24672
llvm-svn: 284267
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Summary:
The main purpose of this new helper is to enable simplifying operations that
have multiple uses. SimplifyDemandedBits does not handle multiple uses
currently, and this new function makes it possible to optimize:
and v1, v0, 0xffffff
mul24 v2, v1, v1 ; Multiply ignoring high 8-bits.
To:
mul24 v2, v0, v0
Where before this would not be optimized, because v1 has multiple uses.
Reviewers: bogner, arsenm
Subscribers: nhaehnle, wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D24964
llvm-svn: 284266
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llvm-svn: 284264
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llvm-svn: 284262
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X86. The pass optimizes as a unit the entire wide load + shuffles pattern
produced by interleaved vectorization. This initial patch optimizes one pattern
(64-bit elements interleaved by a factor of 4). Future patches will generalize
to additional patterns.
Patch by Farhana Aleen
Differential revision: http://reviews.llvm.org/D24681
llvm-svn: 284260
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Summary: The hardware doesn't support this.
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D25523
llvm-svn: 284257
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Use PackedRegisterRef to store the register information in the graph nodes.
This commit also removes support for virtual registers. It has never been
tested or used. It will be possible to add it back if there is a need.
llvm-svn: 284255
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Patch by Michael LeMay
Differential revision: http://reviews.llvm.org/D19852
llvm-svn: 284254
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TargetMachine," as it's causing sanitizer/memory issues until I
can track down this set.
This reverts commit r284203
llvm-svn: 284252
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