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* [X86][XOP] Fix VPERMIL2PD mask creation on 32-bit targetsSimon Pilgrim2016-09-092-73/+160
| | | | | | Use getConstVector helper to correctly create v2i64/v4i64 constants on 32-bit targets llvm-svn: 281105
* [Hexagon] Fix disassembler crash after r279255Krzysztof Parzyszek2016-09-092-0/+10
| | | | | | | When p0 was added as an explicit operand to the duplex subinstructions, the disassembler was not updated to reflect this. llvm-svn: 281104
* [X86] Regenerate test. NFC.Michael Kuperstein2016-09-091-3/+9
| | | | llvm-svn: 281099
* Enable in-tree builds of parallel-libs.Justin Lebar2016-09-091-1/+3
| | | | | | | | | | | | | | Summary: parallel-libs needs its own changes to make this work; these are just the LLVM changes. Reviewers: jhen Subscribers: llvm-commits, beanz, jprice Differential Revision: https://reviews.llvm.org/D24402 llvm-svn: 281097
* Create phi nodes for swifterror values at the end of the phi instructions listArnold Schwaighofer2016-09-092-1/+20
| | | | | | | | ISel makes assumption about the order of phi nodes. rdar://28190150 llvm-svn: 281095
* [NVPTX] Implement llvm.fabs.f32, llvm.max.f32, etc.Justin Lebar2016-09-094-17/+394
| | | | | | | | | | | | | | | | | | | | Summary: Previously these only worked via NVPTX-specific intrinsics. This change will allow us to convert these target-specific intrinsics into the general LLVM versions, allowing existing LLVM passes to reason about their behavior. It also gets us some minor codegen improvements as-is, from situations where we canonicalize code into one of these llvm intrinsics. Reviewers: majnemer Subscribers: llvm-commits, jholewinski, tra Differential Revision: https://reviews.llvm.org/D24300 llvm-svn: 281092
* ARM: move the builtins libcall CC setupSaleem Abdulrasool2016-09-093-166/+171
| | | | | | | | | Move the target specific setup into the target specific lowering setup. As pointed out by Anton, the initial change was moving this too high up the stack resulting in a violation of the layering (the target generic code path setup target specific bits). Sink this into the ARM specific setup. NFC. llvm-svn: 281088
* [cmake] Fix a stale comment from an earlier version of r281085. NFC.Michael Gottesman2016-09-091-2/+1
| | | | llvm-svn: 281086
* [cmake] Export gtest/gtest_main and its dependencies via a special build ↵Michael Gottesman2016-09-095-14/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tree only cmake exports file. Previously, gtest/gtest_main were not exported via cmake. The intention here was to ensure that users whom are linking against the LLVM install tree would not get the gtest/gtest_main targets. This prevents downstream projects that link against the LLVM build tree (i.e. Swift) from getting this dependency information in their cmake builds. Without such dependency information, linker issues can result on linux due to LLVMSupport being put before gtest on the linker command line. This commit preserves behavior that we want for the install tree, while adding support for the build tree by: 1. The special casing for gtest/gtest_main in the add_llvm_library code is removed in favor of a flag called "BUILDTREE_ONLY". If this is set, then the library is communicating that it is only meant to be exported into the build tree and is not meant to be installed or exported via the install tree. This part is just a tweak to remove the special case, the underlying code is the same. 2. The cmake code that exports cmake targets for the build tree has special code to import an additional targets file called LLVMBuildTreeOnlyExports.cmake. Additionally the extra targets are added to the LLVMConfig.cmake's LLVM_EXPORTED_TARGETS variable. In contrast, the "installation" cmake file uses the normal LLVM_EXPORTS_TARGETS as before and does not include the extra exports file. This is implemented by defining/undefining variables when performing a configure of the build/install tree LLVMConfig.cmake files. llvm-svn: 281085
* Add a lower level zlib::uncompress.Rafael Espindola2016-09-092-6/+16
| | | | | | | | | | | SmallVectors are convenient, but they don't cover every use case. In particular, they are fairly large (3 pointers + one element) and there is no way to take ownership of the buffer to put it somewhere else. This patch then adds a lower lever interface that works with any buffer. llvm-svn: 281082
* AMDGPU : Fix mqsad_u32_u8 instruction incorrect data type.Wei Ding2016-09-097-22/+66
| | | | | | Differential Revision: http://reviews.llvm.org/D23700 llvm-svn: 281081
* AMDGPU/SI: Make sure llvm.amdgcn.implicitarg.ptr() is 8-byte aligned for HSATom Stellard2016-09-093-2/+7
| | | | | | | | | | Reviewers: arsenm Subscribers: arsenm, wdng, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D24405 llvm-svn: 281080
* [pdb] Print out some more info when dumping a raw stream.Zachary Turner2016-09-094-26/+60
| | | | | | | | | | | | | | | We have various command line options that print the type of a stream, the size of a stream, etc but nowhere that it can all be viewed together. Since a previous patch introduced the ability to dump the bytes of a stream, this seems like a good place to present a full view of the stream's properties including its size, what kind of data it represents, and the blocks it occupies. So I added the ability to print that information to the -stream-data command line option. llvm-svn: 281077
* [llvm-cov] Remove some asserts in the html renderer (NFC)Vedant Kumar2016-09-091-5/+1
| | | | | | | | | | | These asserts are making tests fragile. The renderer does not enter an invalid state when they fail, however, it may spit out a garbled coverage report because the source text no longer matches the provided coverage mapping. Another follow-up to r281072. llvm-svn: 281076
* Do not widen load for different variable in GVN.Dehao Chen2016-09-097-54/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Widening load in GVN is too early because it will block other optimizations like PRE, LICM. https://llvm.org/bugs/show_bug.cgi?id=29110 The SPECCPU2006 benchmark impact of this patch: Reference: o2_nopatch (1): o2_patched Benchmark Base:Reference (1) ------------------------------------------------------- spec/2006/fp/C++/444.namd 25.2 -0.08% spec/2006/fp/C++/447.dealII 45.92 +1.05% spec/2006/fp/C++/450.soplex 41.7 -0.26% spec/2006/fp/C++/453.povray 35.65 +1.68% spec/2006/fp/C/433.milc 23.79 +0.42% spec/2006/fp/C/470.lbm 41.88 -1.12% spec/2006/fp/C/482.sphinx3 47.94 +1.67% spec/2006/int/C++/471.omnetpp 22.46 -0.36% spec/2006/int/C++/473.astar 21.19 +0.24% spec/2006/int/C++/483.xalancbmk 36.09 -0.11% spec/2006/int/C/400.perlbench 33.28 +1.35% spec/2006/int/C/401.bzip2 22.76 -0.04% spec/2006/int/C/403.gcc 32.36 +0.12% spec/2006/int/C/429.mcf 41.04 -0.41% spec/2006/int/C/445.gobmk 26.94 +0.04% spec/2006/int/C/456.hmmer 24.5 -0.20% spec/2006/int/C/458.sjeng 28 -0.46% spec/2006/int/C/462.libquantum 55.25 +0.27% spec/2006/int/C/464.h264ref 45.87 +0.72% geometric mean +0.23% For most benchmarks, it's a wash, but we do see stable improvements on some benchmarks, e.g. 447,453,482,400. Reviewers: davidxl, hfinkel, dberlin, sanjoy, reames Subscribers: gberry, junbuml Differential Revision: https://reviews.llvm.org/D24096 llvm-svn: 281074
* Fix another -Wunused-variable for non-assert build.Rui Ueyama2016-09-091-3/+4
| | | | llvm-svn: 281073
* [llvm-cov] Try to fix the native_separators.c test some moreVedant Kumar2016-09-091-1/+1
| | | | | | | | | | | | | It's still breaking this bot (though, it looks like it always had been): http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015 This time, add quotes around llvm-{cov,config} so that lit won't expand them. Thanks to Reid for suggesting the patch! llvm-svn: 281072
* [pdb] Add command line options for dumping individual streams and blocksZachary Turner2016-09-097-193/+148
| | | | | | | | | | | | | I ran into a situation where I wanted to print out the contents of page 6 of a PDB as a binary blob, and there was no straightforward way to do that. In addition to adding that, this patch also adds the ability to dump a stream by index as a binary blob, and it will stitch together all the blocks and dump the whole thing as one seemingly contiguous sequence of bytes. llvm-svn: 281070
* Fix -Wunused-variable for non-assert build.Rui Ueyama2016-09-091-3/+2
| | | | llvm-svn: 281069
* [pdb] Pass CVRecord's through the visitor as non-const references.Zachary Turner2016-09-0915-162/+139
| | | | | | | | | | | | | | | | | | This simplifies a lot of code, and will actually be necessary for an upcoming patch to serialize TPI record hash values. The idea before was that visitors should be examining records, not modifying them. But this is no longer true with a visitor that constructs a CVRecord from Yaml. To handle this until now, we were doing some fixups on CVRecord objects at a higher level, but the code is really awkward, and it makes sense to just have the visitor write the bytes into the CVRecord. In doing so I uncovered a few bugs related to `Data` and `RawData` and fixed those. Reviewed By: rnk Differential Revision: https://reviews.llvm.org/D24362 llvm-svn: 281067
* [libFuzzer] one more puzzle, value_profile cracks it in a secondKostya Serebryany2016-09-093-0/+25
| | | | llvm-svn: 281066
* [pdb] Write PDB TPI Stream from Yaml.Zachary Turner2016-09-0930-148/+635
| | | | | | | | | | This writes the full sequence of type records described in Yaml to the TPI stream of the PDB file. Reviewed By: rnk Differential Revision: https://reviews.llvm.org/D24316 llvm-svn: 281063
* [llvm-cov] Handle native paths correctly in the text indexVedant Kumar2016-09-091-1/+5
| | | | | | | | | | Treat filenames the same way in the text index as we do in the html index. This is a follow-up to r281008 (an attempt to unbreak the native_separators.c test on Windows). Patch by Maggie Yi! llvm-svn: 281062
* Move the ocaml_all target into the Misc folder for cleanliness; NFC.Aaron Ballman2016-09-091-0/+1
| | | | llvm-svn: 281061
* [codeview] Don't assert if the array element type is incompleteReid Kleckner2016-09-092-15/+166
| | | | | | | | | This can happen when the frontend knows the debug info will be emitted somewhere else. Usually this happens for dynamic classes with out of line constructors or key functions, but it can also happen when modules are enabled. llvm-svn: 281060
* [Bitcode] Add compatibility test for the 3.9 releaseVedant Kumar2016-09-092-0/+1664
| | | | | | | Fork off compatibility.ll for the 3.9 release. The *.bc file in this commit was produced using a Release build of the release_39 branch. llvm-svn: 281059
* [InstCombine] add tests to show pattern matching failures due to commutationSanjay Patel2016-09-093-0/+148
| | | | | | | I was looking to fix a bug in getComplexity(), and these cases showed up as obvious failures. I'm not sure how to find these in general though. llvm-svn: 281055
* Attempt to fix static_asserts in SelectionDAGNodes.h that MSVC chokes on.Justin Lebar2016-09-091-14/+9
| | | | | | | | These were added in r281051, which, I am embarrassed to admit, has an incomplete commit message that I forgot to update before pushing. You can ignore element (2) in that list. llvm-svn: 281054
* [SelectionDAG] Fix two issues with SDNode::getRawSubclassData().Justin Lebar2016-09-091-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | 1) On some platforms, sizeof(SDNodeBits) == 1, so we were only copying one byte out of the bitfield when we wanted to copy two, and we were leaving half of the return value of getRawSubclassData() undefined. 2) Something something bitfields, not sure exactly what the issue or fix is, yet. (TODO) Summary: Previously we were assuming that SDNodeBits covered all of SDNode's anonymous subclass data bitfield union. But that's not right; it might have size 1, in which it clearly doesn't. This patch adds a field that does cover the whole union and adds static_asserts to ensure it stays correct. Reviewers: ahatanak, chandlerc Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D24223 llvm-svn: 281051
* AMDGPU] Assembler: better support for immediate literals in assembler.Sam Kolton2016-09-0923-519/+1764
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Prevously assembler parsed all literals as either 32-bit integers or 32-bit floating-point values. Because of this we couldn't support f64 literals. E.g. in instruction "v_fract_f64 v[0:1], 0.5", literal 0.5 was encoded as 32-bit literal 0x3f000000, which is incorrect and will be interpreted as 3.0517578125E-5 instead of 0.5. Correct encoding is inline constant 240 (optimal) or 32-bit literal 0x3FE00000 at least. With this change the way immediate literals are parsed is changed. All literals are always parsed as 64-bit values either integer or floating-point. Then we convert parsed literals to correct form based on information about type of operand parsed (was literal floating or binary) and type of expected instruction operands (is this f32/64 or b32/64 instruction). Here are rules how we convert literals: - We parsed fp literal: - Instruction expects 64-bit operand: - If parsed literal is inlinable (e.g. v_fract_f64_e32 v[0:1], 0.5) - then we do nothing this literal - Else if literal is not-inlinable but instruction requires to inline it (e.g. this is e64 encoding, v_fract_f64_e64 v[0:1], 1.5) - report error - Else literal is not-inlinable but we can encode it as additional 32-bit literal constant - If instruction expect fp operand type (f64) - Check if low 32 bits of literal are zeroes (e.g. v_fract_f64 v[0:1], 1.5) - If so then do nothing - Else (e.g. v_fract_f64 v[0:1], 3.1415) - report warning that low 32 bits will be set to zeroes and precision will be lost - set low 32 bits of literal to zeroes - Instruction expects integer operand type (e.g. s_mov_b64_e32 s[0:1], 1.5) - report error as it is unclear how to encode this literal - Instruction expects 32-bit operand: - Convert parsed 64 bit fp literal to 32 bit fp. Allow lose of precision but not overflow or underflow - Is this literal inlinable and are we required to inline literal (e.g. v_trunc_f32_e64 v0, 0.5) - do nothing - Else report error - Do nothing. We can encode any other 32-bit fp literal (e.g. v_trunc_f32 v0, 10000000.0) - Parsed binary literal: - Is this literal inlinable (e.g. v_trunc_f32_e32 v0, 35) - do nothing - Else, are we required to inline this literal (e.g. v_trunc_f32_e64 v0, 35) - report error - Else, literal is not-inlinable and we are not required to inline it - Are high 32 bit of literal zeroes or same as sign bit (32 bit) - do nothing (e.g. v_trunc_f32 v0, 0xdeadbeef) - Else - report error (e.g. v_trunc_f32 v0, 0x123456789abcdef0) For this change it is required that we know operand types of instruction (are they f32/64 or b32/64). I added several new register operands (they extend previous register operands) and set operand types to corresponding types: ''' enum OperandType { OPERAND_REG_IMM32_INT, OPERAND_REG_IMM32_FP, OPERAND_REG_INLINE_C_INT, OPERAND_REG_INLINE_C_FP, } ''' This is not working yet: - Several tests are failing - Problems with predicate methods for inline immediates - LLVM generated assembler parts try to select e64 encoding before e32. More changes are required for several AsmOperands. Reviewers: vpykhtin, tstellarAMD Subscribers: arsenm, kzhuravl, artem.tamazov Differential Revision: https://reviews.llvm.org/D22922 llvm-svn: 281050
* [Sparc][LEON] Removed the parts of the errata fixes implemented using inline ↵Chris Dewhurst2016-09-094-144/+9
| | | | | | assembly as this is not the desired behaviour for end-users. Small change to a unit test to implement this without requiring the inline assembly. llvm-svn: 281047
* [ARM] ADD with a negative offset can become SUB for freeJames Molloy2016-09-092-0/+21
| | | | | | So model that directly in TTI::getIntImmCost(). llvm-svn: 281044
* [ARM] icmp %x, -C can be lowered to a simple ADDS or CMNJames Molloy2016-09-092-0/+45
| | | | | | Tell TargetTransformInfo about this so ConstantHoisting is informed. llvm-svn: 281043
* [SelectionDAG] Ensure DAG::getZeroExtendInReg is called with a scalar typeSimon Pilgrim2016-09-093-3/+110
| | | | | | Fixes issue with rL280927 identified by Mikael Holmén llvm-svn: 281042
* [Thumb] Select (CMPZ X, -C) -> (CMPZ (ADDS X, C), 0)James Molloy2016-09-096-6/+81
| | | | | | The CMPZ #0 disappears during peepholing, leaving just a tADDi3, tADDi8 or t2ADDri. This avoids having to materialize the expensive negative constant in Thumb-1, and allows a shrinking from a 32-bit CMN to a 16-bit ADDS in Thumb-2. llvm-svn: 281040
* GlobalISel: remove G_TYPE and G_PHITim Northover2016-09-0918-60/+21
| | | | | | | | These instructions were only necessary when type information was stored in the MachineInstr (because only generic MachineInstrs possessed a type). Now that it's in MachineRegisterInfo, COPY and PHI work fine. llvm-svn: 281037
* GlobalISel: fix comments and add assertions for valid instructions.Tim Northover2016-09-092-56/+175
| | | | llvm-svn: 281036
* GlobalISel: move type information to MachineRegisterInfo.Tim Northover2016-09-0950-1310/+1220
| | | | | | | | | | | | | | | | | We want each register to have a canonical type, which means the best place to store this is in MachineRegisterInfo rather than on every MachineInstr that happens to use or define that register. Most changes following from this are pretty simple (you need an MRI anyway if you're going to be doing any transformations, so just check the type there). But legalization doesn't really want to check redundant operands (when, for example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's operand type field to encode these constraints and limit legalization's work. As an added bonus, more validation is possible, both in MachineVerifier and MachineIRBuilder (coming soon). llvm-svn: 281035
* Revert "[mips] Fix c.<cc>.<fmt> instruction definition."Simon Dardis2016-09-0937-948/+614
| | | | | | | This reverts commit r281022. Mips buildbot broke, due to unhandled register class FCC. llvm-svn: 281033
* [AMDGPU] Assembler: rename amd_kernel_code_t asm names according to specSam Kolton2016-09-099-430/+273
| | | | | | | | | | | | | | Summary: Also removed duplicate code from AMDGPUTargetAsmStreamer. This change only change how amd_kernel_code_t is parsed and printed. No variable names are changed. Reviewers: vpykhtin, tstellarAMD Subscribers: arsenm, wdng, nhaehnle Differential Revision: https://reviews.llvm.org/D24296 llvm-svn: 281028
* [Thumb1] Teach optimizeCompareInstr about thumb1 comparesJames Molloy2016-09-093-9/+78
| | | | | | | | This avoids us doing a completely unneeded "cmp r0, #0" after a flag-setting instruction if we only care about the Z or C flags. Add LSL/LSR to the whitelist while we're here and add testing. This code could really do with a spring clean. llvm-svn: 281027
* [AMDGPU] Assembler: match e32 VOP instructions before e64.Sam Kolton2016-09-097-32/+126
| | | | | | | | | | | | | | | | | | | Summary: Split assembler match table in 4 tables with assembler variants: Default - all instructions except VOP3, SDWA and DPP - VOP3 - SDWA - DPP First match Default table then VOP3, SDWA and DPP. Reviewers: tstellarAMD, artem.tamazov, vpykhtin Subscribers: arsenm, wdng, nhaehnle, AMDGPU Differential Revision: https://reviews.llvm.org/D24252 llvm-svn: 281023
* [mips] Fix c.<cc>.<fmt> instruction definition.Simon Dardis2016-09-0937-614/+948
| | | | | | | | | | | | | | | As part of this effort, remove MipsFCmp nodes and use tablegen patterns rather than custom lowering through C++. Unexpectedly, this improves codesize for microMIPS as previous floating point setcc expansions would materialize 0 and 1 into GPRs before using the relevant mov[tf].[sd] instruction. Now $zero is used directly. Reviewers: dsanders, vkalintiris, zoran.jovanovic Differential Review: https://reviews.llvm.org/D23118 llvm-svn: 281022
* [Sparc][LEON] Unit test for CASA instruction supported by some LEON ↵Chris Dewhurst2016-09-091-0/+14
| | | | | | processors added. llvm-svn: 281021
* [Coroutines] Part13: Handle single edge PHINodes across suspendsGor Nishanov2016-09-094-4/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: If one of the uses of the value is a single edge PHINode, handle it. Original: %val = something <suspend> %p = PHINode [%val] After Spill + Part13: %val = something %slot = gep val.spill.slot store %val, %slot <suspend> %p = load %slot Plus tiny fixes/changes: * use correct index for coro.free in CoroCleanup * fixup id parameter in coro.free to allow authoring coroutine in plain C with __builtins Reviewers: majnemer Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D24242 llvm-svn: 281020
* Rationalise the attribute getter/setter methods on Function and CallSite.Amaury Sechet2016-09-097-97/+51
| | | | | | | | | | | | | | | | | | | Summary: While woring on mapping attributes in the C API, it clearly appeared that the recent changes in the API on the C++ side left Function and Call/Invoke with an attribute API that grew in an ad hoc manner. This makes it difficult to work with it, because one doesn't know which overloads exists and which do not. Make sure that getter/setter function exists for both enum and string version. Remove inconsistent getter/setter, unless they have many callsites. This should make it easier to work with attributes in the future. This doesn't change how attribute works. Reviewers: bkramer, whitequark, mehdi_amini, void Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D21514 llvm-svn: 281019
* [libFuzzer] improve -print_pcs to not print new PCs coming from libFuzzer itselfKostya Serebryany2016-09-092-8/+19
| | | | llvm-svn: 281016
* [libFuzzer] remove unneeded callKostya Serebryany2016-09-092-9/+0
| | | | llvm-svn: 281014
* [AVX-512] Add VPCMP instructions to the load folding tables and make them ↵Craig Topper2016-09-093-13/+63
| | | | | | commutable. llvm-svn: 281013
* [AVX-512] Add more integer vector comparison tests with loads. Some of these ↵Craig Topper2016-09-091-0/+198
| | | | | | | | show opportunities where we can commute to fold loads. Commutes will be added in a followup commit. llvm-svn: 281012
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