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* x86 / Darwin PIC support.Evan Cheng2006-02-1810-36/+143
| | | | llvm-svn: 26273
* Moved PICEnabled to include/llvm/Target/TargetOptions.hEvan Cheng2006-02-184-1/+3
| | | | llvm-svn: 26272
* Move PICEnabled declaration here.Evan Cheng2006-02-181-0/+6
| | | | llvm-svn: 26271
* Fix a tricky issue in the SimplifyDemandedBits code where CombineTo wasn'tChris Lattner2006-02-172-9/+95
| | | | | | | exactly the API we wanted to call into. This fixes the crash on crafty last night. llvm-svn: 26269
* add a new methodChris Lattner2006-02-171-0/+7
| | | | llvm-svn: 26268
* A few final (for now) testsNate Begeman2006-02-172-0/+16
| | | | llvm-svn: 26267
* Yet another testNate Begeman2006-02-171-0/+9
| | | | llvm-svn: 26266
* New tests!Nate Begeman2006-02-173-0/+34
| | | | llvm-svn: 26265
* Added documentation for vset and vselect.Robert Bocchino2006-02-171-4/+158
| | | | llvm-svn: 26264
* Clean up DemandedBitsAreZero interfaceNate Begeman2006-02-171-22/+26
| | | | | | | Make more use of the new mask helpers in valuetypes.h Combine (sra (srl x, c1), c1) -> sext_inreg if legal llvm-svn: 26263
* Fix a nit sabre noticedNate Begeman2006-02-171-1/+1
| | | | llvm-svn: 26262
* Don't expand sdiv by power of two before legalize, since it will likelyNate Begeman2006-02-171-2/+2
| | | | | | generate illegal nodes. llvm-svn: 26261
* unbreak the buildChris Lattner2006-02-171-1/+0
| | | | llvm-svn: 26260
* Unbreak x86 beEvan Cheng2006-02-171-17/+22
| | | | llvm-svn: 26259
* Fix loops where the header has an exit, fixing a loop-unswitch crash on craftyChris Lattner2006-02-171-13/+15
| | | | llvm-svn: 26258
* Fix a comment sabre noticed :)Nate Begeman2006-02-172-2/+2
| | | | llvm-svn: 26257
* A couple new regression tests to make sure we always pattern match the newNate Begeman2006-02-172-0/+51
| | | | | | opcodes on ppc. llvm-svn: 26256
* kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBCNate Begeman2006-02-1712-271/+130
| | | | | | | and SUBE nodes that actually expose what's going on and allow for significant simplifications in the targets. llvm-svn: 26255
* Fix another miscompilation exposed by lencode, where we lowered i64->f32Chris Lattner2006-02-171-1/+1
| | | | | | | conversions to __floatdidf instead of __floatdisf on targets that support f32 but not i64 (e.g. sparc). llvm-svn: 26254
* add note about div by power of 2Chris Lattner2006-02-171-0/+32
| | | | llvm-svn: 26253
* Fix bug noticed by VC++.Jeff Cohen2006-02-171-2/+2
| | | | llvm-svn: 26252
* Inform Visual Studio of deleted file.Jeff Cohen2006-02-171-3/+0
| | | | llvm-svn: 26251
* Whoops, didn't mean to check this in yet.Nate Begeman2006-02-171-8/+0
| | | | llvm-svn: 26250
* Add a missing and useful pat fragNate Begeman2006-02-171-2/+9
| | | | llvm-svn: 26249
* start of some new simplification code, not thoroughly tested, use at your ownChris Lattner2006-02-171-14/+161
| | | | | | risk :) llvm-svn: 26248
* Remind ourselves to revisit the "pxor vs. xorps/xorpd to clear XMM registers"Evan Cheng2006-02-171-0/+6
| | | | | | issue. Need to do more experiments. llvm-svn: 26247
* Kill the x86 pattern isel. boom.Nate Begeman2006-02-174-3973/+211
| | | | llvm-svn: 26246
* Remove the entry about using movapd for SSE reg-reg moves.Evan Cheng2006-02-171-6/+0
| | | | llvm-svn: 26245
* pxor (for FLD0SS) encoding was missing the OpSize prefix.Evan Cheng2006-02-161-1/+1
| | | | llvm-svn: 26244
* Remove the skeleton target, it doesn't produce useful code and there areChris Lattner2006-02-1614-614/+0
| | | | | | | other small targets that do that can be learned from. They also have the added advantage of being tested :) llvm-svn: 26243
* Dumb bug. Code sees a memcpy from X+c so it increments src offset. But itEvan Cheng2006-02-161-4/+10
| | | | | | | turns out not to point to a constant string but it forgot change the offset back. llvm-svn: 26242
* 1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. ThisEvan Cheng2006-02-163-13/+29
| | | | | | | | | | | proves to be worth 20% on Ptrdist/ks. Might be related to dependency breaking support. 2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These are used for FR32 / FR64 reg-to-reg copies. 3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to spill / restore FsMOVAPSrr and FsMOVAPDrr. llvm-svn: 26241
* Use movaps / movapd to spill / restore V4F4 / V2F8 registers.Evan Cheng2006-02-161-4/+12
| | | | llvm-svn: 26240
* remove skeleton targetChris Lattner2006-02-161-2/+1
| | | | llvm-svn: 26239
* Rework the SelectionDAG-based implementations of SimplifyDemandedBitsNate Begeman2006-02-167-201/+625
| | | | | | | and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
* don't build the skeleton targetChris Lattner2006-02-161-2/+1
| | | | llvm-svn: 26237
* remove support for the skeleton targetChris Lattner2006-02-161-5/+0
| | | | llvm-svn: 26236
* Change SplitBlock to increment a BasicBlock::iterator, not an Instruction*. ↵Chris Lattner2006-02-161-23/+27
| | | | | | | | | | | Apparently they do different things :) This fixes a testcase that nate reduced from spass. Also included are a couple minor code changes that don't affect the generated code at all. llvm-svn: 26235
* MOVAPSrr and MOVAPDrr instruction format should be MRMSrcReg.Evan Cheng2006-02-161-2/+2
| | | | llvm-svn: 26234
* distinguish between objects and register names, now we can have stuffDuraid Madina2006-02-161-6/+12
| | | | | | | | with names like "f84", "in6" etc etc. this should fix one or two tests llvm-svn: 26232
* If the false case is the current basic block, then this is a self loop.Evan Cheng2006-02-162-11/+9
| | | | | | | | | | We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra instruction in the loop. Instead, invert the condition and emit "Loop: ... br!cond Loop; br Out. Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering. llvm-svn: 26231
* Lowering of sdiv X, pow2 was broken, this fixes it. This patch is writtenChris Lattner2006-02-161-6/+12
| | | | | | by Nate, I'm just committing it for him. llvm-svn: 26230
* Fix a minor makefile bug with lex/yacc handling that nate noticed. We don'tChris Lattner2006-02-161-2/+2
| | | | | | | | want to copy the files when the .cpp file changes, we want to copy them to the .cvs versions when the .l/.y file change (like the comments even say). This avoids having bogus changes show up in diffs. llvm-svn: 26229
* Fix VC++ warning.Jeff Cohen2006-02-161-1/+0
| | | | llvm-svn: 26228
* Visual Studio enters the future of bisoning.Jeff Cohen2006-02-161-2/+2
| | | | llvm-svn: 26227
* Use movaps / movapd (instead of movss / movsd) to do FR32 / FR64 reg to regEvan Cheng2006-02-161-2/+2
| | | | | | | | | | | | | | | | | transfer. According to the Intel P4 Optimization Manual: Moves that write a portion of a register can introduce unwanted dependences. The movsd reg, reg instruction writes only the bottom 64 bits of a register, not to all 128 bits. This introduces a dependence on the preceding instruction that produces the upper 64 bits (even if those bits are not longer wanted). The dependence inhibits register renaming, and thereby reduces parallelism. Not to mention movaps is shorter than movss. llvm-svn: 26226
* fix a bug where we unswitched the wrong wayChris Lattner2006-02-161-2/+2
| | | | llvm-svn: 26225
* A bit more memset / memcpy optimization.Evan Cheng2006-02-163-7/+53
| | | | | | | Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned, 2) size is not known to be greater or equal to some minimum value (currently 128). llvm-svn: 26224
* Implement trivial unswitching for switch stmts. This allows us to trivialChris Lattner2006-02-151-27/+51
| | | | | | | | | | | | | | | | | | unswitch this loop on 2 before sweating to unswitch on 1/3. void test4(int N, int i, int C, int*P, int*Q) { int j; for (j = 0; j < N; ++j) { switch (C) { // general unswitching. default: P[i+j] = 0; break; case 1: Q[i+j] = 0; break; case 3: P[i+j] = Q[i+j]; break; case 2: break; // TRIVIAL UNSWITCH on C==2 } } } llvm-svn: 26223
* Remove an entry.Evan Cheng2006-02-151-8/+0
| | | | llvm-svn: 26222
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