summaryrefslogtreecommitdiffstats
path: root/llvm
Commit message (Collapse)AuthorAgeFilesLines
...
* MachineVerifier: Check that SlotIndex MBBIndexList is sorted.Matthias Braun2015-09-091-0/+17
| | | | | | | This introduces a check that the MBBIndexList is sorted as proposed in http://reviews.llvm.org/D12443 but split up into a separate commit. llvm-svn: 247166
* AMDGPU: Extract full 64-bit subregister and use subregsMatt Arsenault2015-09-091-35/+29
| | | | | | | | | | | | Instead of extracting both 32-bit components from the 128-bit register. This produces fewer copies and is easier for the copy peephole optimizer to understand and see the actual uses as extracts from a reg_sequence. This avoids needing to handle subregister composing in the PeepholeOptimizer's ValueTracker for this case. llvm-svn: 247162
* AMDGPU: Remove unused multiclass argumentMatt Arsenault2015-09-091-5/+4
| | | | llvm-svn: 247161
* llvm-config: Add --build-system optionTom Stellard2015-09-094-0/+8
| | | | | | | | | | | | | | | Summary: This can be used for distinguishing between cmake and autoconf builds. Users may need this in order to handle inconsistencies between the outputs of the two build systems. Reviewers: echristo, chandlerc, beanz Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11838 llvm-svn: 247159
* [WebAssembly] Implement calls with void return types.Dan Gohman2015-09-095-8/+27
| | | | llvm-svn: 247158
* AMDGPU/SI: Fold operands through REG_SEQUENCE instructionsTom Stellard2015-09-094-14/+27
| | | | | | | | | | | | | | Summary: This helps mostly when we use add instructions for address calculations that contain immediates. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D12256 llvm-svn: 247157
* [CostModel][AArch64] Remove amortization factor for some of the vector ↵Silviu Baranga2015-09-092-10/+11
| | | | | | | | | | | | | | | | | select instructions Summary: We are not scalarizing the wide selects in codegen for i16 and i32 and therefore we can remove the amortization factor. We still have issues with i64 vectors in codegen though. Reviewers: mcrosier Subscribers: mcrosier, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D12724 llvm-svn: 247156
* don't repeat function names in comments; NFCSanjay Patel2015-09-094-33/+27
| | | | llvm-svn: 247154
* [WebAssembly] Tidy up some unneeded newline characters.Dan Gohman2015-09-091-10/+9
| | | | llvm-svn: 247152
* [CMake] Flag recursive cmake invocations for cross-compileJoseph Tremoulet2015-09-092-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Cross-compilation uses recursive cmake invocations to build native host tools. These recursive invocations only forward a fixed set of variables/options, since the native environment is generally the default. This change adds -DLLVM_TARGET_IS_CROSSCOMPILE_HOST=TRUE to the recursive cmake invocations, so that cmake files can distinguish these recursive invocations from top-level ones, which can explain why expected options are unset. LLILC will use this to avoid trying to generate its build rules in the crosscompile native host target (where it is not needed), which would fail if attempted because LLILC requires a cmake variable passed on the command line, which is not forwarded in the recursive invocation. Reviewers: rnk, beanz Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12679 llvm-svn: 247151
* function names start with a lower case letter; NFCSanjay Patel2015-09-091-54/+54
| | | | llvm-svn: 247150
* AVX512: Implemented encoding and intrinsics forIgor Breger2015-09-0912-89/+1145
| | | | | | | | | vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11802 llvm-svn: 247149
* don't repeat function names in comments; NFCSanjay Patel2015-09-091-35/+32
| | | | llvm-svn: 247148
* [mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and ↵Zoran Jovanovic2015-09-097-11/+141
| | | | | | | | SRL16 instructions Differential Revision: http://reviews.llvm.org/D11178 llvm-svn: 247146
* Fix PR 24633 - Handle undef values when parsing standalone constants.Alex Lorenz2015-09-093-0/+21
| | | | llvm-svn: 247145
* Rename ExitCount to BackedgeTakenCount, because that's what it is.James Molloy2015-09-091-8/+9
| | | | | | We called a variable ExitCount, stored the backedge count in it, then redefined it to be the exit count again. llvm-svn: 247140
* Delay predication of stores until near the end of vector code generationJames Molloy2015-09-092-65/+62
| | | | | | | | Predicating stores requires creating extra blocks. It's much cleaner if we do this in one pass instead of mutating the CFG while writing vector instructions. Besides which we can make use of helper functions to update domtree for us, reducing the work we need to do. llvm-svn: 247139
* LLVM does not distinguish Cortex-M4 from Cortex-M4F neither Cortex-R5 from R5F.Alexandros Lamprineas2015-09-091-5/+2
| | | | | | | | | | | Removed "cortex-r5f" and "cortex-m4f" from Target Parser, sinced they are unknown cpu names for llvm and clang. Also updated default FPUs for R5 and M4 accordingly. Differential Revision: http://reviews.llvm.org/D12692 Change-Id: Ib81c7216521a361d8ee1296e4b6a2aa00bd479c5 llvm-svn: 247136
* Fix vector splitting for extract_vector_elt and vector elements of <8-bits.Daniel Sanders2015-09-093-2/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: One of the vector splitting paths for extract_vector_elt tries to lower: define i1 @via_stack_bug(i8 signext %idx) { %1 = extractelement <2 x i1> <i1 false, i1 true>, i8 %idx ret i1 %1 } to: define i1 @via_stack_bug(i8 signext %idx) { %base = alloca <2 x i1> store <2 x i1> <i1 false, i1 true>, <2 x i1>* %base %2 = getelementptr <2 x i1>, <2 x i1>* %base, i32 %idx %3 = load i1, i1* %2 ret i1 %3 } However, the elements of <2 x i1> are not byte-addressible. The result of this is that the getelementptr expands to '%base + %idx * (1 / 8)' which simplifies to '%base + %idx * 0', and then simply '%base' causing all values of %idx to extract element zero. This commit fixes this by promoting the vector elements of <8-bits to i8 before splitting the vector. This fixes a number of test failures in pocl. Reviewers: pekka.jaaskelainen Subscribers: pekka.jaaskelainen, llvm-commits Differential Revision: http://reviews.llvm.org/D12591 llvm-svn: 247128
* Fix a typo I spotted when hacking on SROA. Somewhat alarming thatChandler Carruth2015-09-091-1/+1
| | | | | | nothing broke. llvm-svn: 247127
* [mips][microMIPS] Implement CACHEE and PREFE instructionsZoran Jovanovic2015-09-097-8/+67
| | | | | | Differential Revision: http://reviews.llvm.org/D11628 llvm-svn: 247125
* AMDGPU: Fix not encoding src2 of VOP3b instructionsMatt Arsenault2015-09-091-4/+4
| | | | | | | Broken by r247074. Should include an assembler test, but the assembler is currently broken for VOP3b apparently. llvm-svn: 247123
* [IRCE] Add INITIALIZE_PASS_DEPENDENCY invocations.Sanjoy Das2015-09-091-2/+9
| | | | | | IRCE was just using INITIALIZE_PASS(), which is incorrect. llvm-svn: 247122
* [RuntimeDyld] Add support for MachO x86_64 SUBTRACTOR relocation.Lang Hames2015-09-092-1/+63
| | | | llvm-svn: 247119
* [WebAssembly] Fix lowering of calls with more than one argument.Dan Gohman2015-09-092-2/+18
| | | | llvm-svn: 247118
* SelectionDAG: Support Expand of f16 extloadsMatt Arsenault2015-09-095-30/+122
| | | | | | | | | | Currently this hits an assert that extload should always be supported, which assumes integer extloads. This moves a hack out of SI's argument lowering and is covered by existing tests. llvm-svn: 247113
* [WebAssembly] Implement WebAssemblyInstrInfo::copyPhysRegDan Gohman2015-09-094-22/+64
| | | | llvm-svn: 247110
* Fix typos / grammarMatt Arsenault2015-09-092-27/+27
| | | | llvm-svn: 247109
* Revert "Bitcode: ArrayRef-ize EmitRecordWithAbbrev(), NFC"Duncan P. N. Exon Smith2015-09-091-16/+15
| | | | | | | | | | This reverts commit r247107. Turns out clang calls these functions directly, and `ArrayRef<T>` doesn't have a working implicit conversion from `SmallVector<T>`. http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental_build/14247 llvm-svn: 247108
* Bitcode: ArrayRef-ize EmitRecordWithAbbrev(), NFCDuncan P. N. Exon Smith2015-09-091-15/+16
| | | | | | | | Change `EmitRecordWithAbbrev()` and friends to take an `ArrayRef<T>` instead of requiring a `SmallVectorImpl<T>`. No functionality change intended. llvm-svn: 247107
* [llvm-readobj] MachO -- dump LinkerOptions load command.Davide Italiano2015-09-095-49/+63
| | | | | | | | | | | | | | | | | | | | Example output: Linker Options { Size: 32 Count: 2 Strings [ Value: -framework Value: Cocoa ] } There were only two tests using this -- so I converted them as part of this commit rather than separately. Differential Revision: http://reviews.llvm.org/D12702 llvm-svn: 247106
* [WinEH] Avoid creating MBBs for LLVM BBs that cannot contain codeReid Kleckner2015-09-086-63/+83
| | | | | | | | | | | | | | Typically these are catchpads, which hold data used to decide whether to catch the exception or continue unwinding. We also shouldn't create MBBs for catchendpads, cleanupendpads, or terminatepads, since no real code can live in them. This fixes a problem where MI passes (like the register allocator) would try to put code into catchpad blocks, which are not executed by the runtime. In the new world, blocks ending in invokes now have many possible successors. llvm-svn: 247102
* Re-apply r247080 with order of evaluation fix.Peter Collingbourne2015-09-088-144/+559
| | | | llvm-svn: 247095
* [WinEH] Emit prologues and epilogues for funcletsReid Kleckner2015-09-0811-57/+399
| | | | | | | | | | | | | | | | | | | | | | | | Summary: 32-bit funclets have short prologues that allocate enough stack for the largest call in the whole function. The runtime saves CSRs for the funclet. It doesn't restore CSRs after we finally transfer control back to the parent funciton via a CATCHRET, but that's a separate issue. 32-bit funclets also have to adjust the incoming EBP value, which is what llvm.x86.seh.recoverframe does in the old model. 64-bit funclets need to spill CSRs as normal. For simplicity, this just spills the same set of CSRs as the parent function, rather than trying to compute different CSR sets for the parent function and each funclet. 64-bit funclets also allocate enough stack space for the largest outgoing call frame, like 32-bit. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12546 llvm-svn: 247092
* Revert r247080, "LowerBitSets: Extend pass to support functions as bitsetPeter Collingbourne2015-09-088-559/+144
| | | | | | members." as it causes test failures on a number of bots. llvm-svn: 247088
* [Bitcode] Add compatibility tests for new instructionsVedant Kumar2015-09-081-3/+97
| | | | | | | | | Adds basic compatibility tests for the following instructions: catchpad, catchendpad, cleanuppad, cleanupendpad, terminatepad, cleanupret, catchret llvm-svn: 247087
* [docs] Fix typo in catchret exampleVedant Kumar2015-09-081-1/+1
| | | | | | | An example usage of catchret omitted the "to" in "to label" in ExceptionHandling.rst. llvm-svn: 247086
* Fix the PPC CTR Loop pass to look for calls to the intrinsics thatEric Christopher2015-09-082-0/+355
| | | | | | read CTR and count them as reading the CTR. llvm-svn: 247083
* LowerBitSets: Extend pass to support functions as bitset members.Peter Collingbourne2015-09-088-144/+559
| | | | | | | | | | | | | | This change extends the bitset lowering pass to support bitsets that may contain either functions or global variables. A function bitset is lowered to a jump table that is laid out before one of the functions in the bitset. Also add support for non-string bitset identifier names. This allows for distinct metadata nodes to stand in for names with internal linkage, as done in D11857. Differential Revision: http://reviews.llvm.org/D11856 llvm-svn: 247080
* [libFuzzer]Add a test for defeating a hash sum.Ivan Krasin2015-09-083-0/+40
| | | | | | | | | | | | | | | | | Summary: Add a test for a data followed by 4-byte hash value. I use a slightly modified Jenkins hash function, as described in https://en.wikipedia.org/wiki/Jenkins_hash_function The modification is to ensure that hash(zeros) != 0. Reviewers: kcc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12648 llvm-svn: 247076
* AMDGPU/SI: Fix input vcc operand for VOP2b instructionsMatt Arsenault2015-09-086-59/+124
| | | | | | | | | Adds vcc to output string input for e32. Allows option of using e64 encoding with assembler. Also fixes these instructions not implicitly reading exec. llvm-svn: 247074
* [NVPTX] Added run NVVMReflect pass to NVPTX back-end.Artem Belevich2015-09-081-0/+1
| | | | | | | | | The pass is needed to remove __nvvm_reflect calls when we link in libdevice bitcode that comes with CUDA. Differential Revision: http://reviews.llvm.org/D11663 llvm-svn: 247072
* Fix comments and RUN line in x86-64 stdarg test leftover from last commitDerek Schuff2015-09-081-2/+2
| | | | | | From http://reviews.llvm.org/D12346 llvm-svn: 247070
* x32. Fixes a bug in how struct va_list is initialized in x32Derek Schuff2015-09-085-5/+157
| | | | | | | | | | | | | Summary: This patch modifies X86TargetLowering::LowerVASTART so that struct va_list is initialized with 32 bit pointers in x32. It also includes tests that call @llvm.va_start() for x32. Patch by João Porto Subscribers: llvm-commits, hjl.tools Differential Revision: http://reviews.llvm.org/D12346 llvm-svn: 247069
* [libFuzzer] remove a piece of stale codeKostya Serebryany2015-09-081-41/+1
| | | | llvm-svn: 247067
* [libFuzzer] be more robust when dealing with files on disk (e.g. don't crash ↵Kostya Serebryany2015-09-081-4/+2
| | | | | | if a file was there but disappeared) llvm-svn: 247066
* [WebAssembly] Support running without a register allocator in the default ↵Dan Gohman2015-09-082-51/+19
| | | | | | | | | | | | | CodeGen passes This allows backends which don't use a traditional register allocator, but do need PHI lowering and other passes, to use the default TargetPassConfig::addFastRegAlloc and TargetPassConfig::addOptimizedRegAlloc implementations. Differential Revision: http://reviews.llvm.org/D12691 llvm-svn: 247065
* Add const overload of findRegisterUseOperandMatt Arsenault2015-09-081-0/+7
| | | | llvm-svn: 247063
* [docs] Update documentation for the landingpad instructionVedant Kumar2015-09-081-5/+5
| | | | llvm-svn: 247062
* refactor matches for De Morgan's Laws; NFCISanjay Patel2015-09-081-17/+32
| | | | llvm-svn: 247061
OpenPOWER on IntegriCloud