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* [Mem2Reg] Clang-format unformatted parts of this file. NFCI.Davide Italiano2017-11-271-28/+23
| | | | llvm-svn: 319097
* [SROA] Propagate !range metadata when moving loads.Davide Italiano2017-11-274-32/+188
| | | | | | | | | | | | | This tries to propagate !range metadata to a pre-existing load when a load is optimized out. This is done instead of adding an assume because converting loads to and from assumes creates a lot of IR. Patch by Ariel Ben-Yehuda. Differential Revision: https://reviews.llvm.org/D37216 llvm-svn: 319096
* [PartiallyInlineLibCalls][x86] add TTI hook to allow sqrt inlining to depend ↵Sanjay Patel2017-11-279-25/+58
| | | | | | | | | | | on arg rather than result This should fix PR31455: https://bugs.llvm.org/show_bug.cgi?id=31455 Differential Revision: https://reviews.llvm.org/D28314 llvm-svn: 319094
* Add release note about TargetRegistry change from r318352Daniel Sanders2017-11-271-0/+5
| | | | llvm-svn: 319093
* [AMDGPU] Update test nullptr.ll to use amdgiz environmentYaxun Liu2017-11-271-57/+63
| | | | | | | | | | This test needs to be manually updated since it is difficult to do it with script. Addr space 6 to 23 are only used by r600, therefore only check them for r600. Differential Revision: https://reviews.llvm.org/D40117 llvm-svn: 319092
* COFF: Do not create SectionChunks for discarded comdat sections.Peter Collingbourne2017-11-271-0/+14
| | | | | | | | | | | | | | | | | | | | With this change, instead of creating a SectionChunk for each section in the object file, we only create them when we encounter a prevailing comdat section. Also change how symbol resolution occurs between comdat symbols. Now only the comdat leader participates in comdat resolution, and not any other external associated symbols. This is more in line with how COFF semantics are defined, and should allow for a more straightforward implementation of non-ANY comdat types. On my machine, this change reduces our runtime linking a release build of chrome_child.dll with /nopdb from 5.65s to 4.54s (median of 50 runs). Differential Revision: https://reviews.llvm.org/D40238 llvm-svn: 319090
* Use LIST_SEPARATOR rather than escaping in ExternalProject_AddPetr Hosek2017-11-271-1/+2
| | | | | | | | | | | Escaping ; in list arguments passed to ExternalProject_Add doesn't seem to be working in newer versions of CMake (see https://public.kitware.com/Bug/view.php?id=16137 for more details). Use a custom LIST_SEPARATOR instead which is the officially supported way. Differential Revision: https://reviews.llvm.org/D40232 llvm-svn: 319089
* [PowerPC] Remove redundant TOC savesZaara Syeda2017-11-274-2/+210
| | | | | | | | | | This patch adds a peep hole optimization to remove any redundant toc save instructions added as part of the call sequence for indirect calls. It removes any toc saves within a function that are dominated by another toc save. Differential Revision: https://reviews.llvm.org/D39736 llvm-svn: 319087
* Rename MCTargetOptionsCommandFlags.h to .def as it is not a normal/modular ↵David Blaikie2017-11-277-21/+20
| | | | | | header as much as it is for stamping out some global/static variables llvm-svn: 319086
* [SelectionDAG] Add a debug message when vector_shuffle nodes are created.Craig Topper2017-11-271-1/+3
| | | | | | We print a debug message when most nodes are created, but getVectorShuffle was missing. llvm-svn: 319085
* Rename CommandFlags.h -> CommandFlags.defDavid Blaikie2017-11-2711-392/+371
| | | | | | | | | Since this isn't a real header - it includes static functions and had external linkage variables (though this change makes them static, since that's what they should be) so can't be included more than once in a program. llvm-svn: 319082
* Fix -Werror build for signed/unsigned comparison with use of explicit ↵David Blaikie2017-11-271-10/+10
| | | | | | unsigned literals llvm-svn: 319081
* Revert r319069 - [cmake] Pass -Wl,-z,nodelete on Linux to prevent unloadingMichal Gorny2017-11-271-8/+0
| | | | | | This breaks one of the unit tests. Need to find a good solution. llvm-svn: 319076
* Inliner: Don't mark notail calls with the 'tail' attributeArnold Schwaighofer2017-11-272-1/+17
| | | | | | | | | | | | enum TailCallKind { TCK_None = 0, TCK_Tail = 1, TCK_MustTail = 2, TCK_NoTail = 3 }; TCK_NoTail is greater than TCK_Tail so taking the min does not do the correct thing. rdar://35639547 llvm-svn: 319075
* Add opt-viewer testingAdam Nemet2017-11-2712-0/+1152
| | | | | | | | | | | | | | | Detects whether we have the Python modules (pygments, yaml) required by opt-viewer and hooks this up to REQUIRES. This fixes https://bugs.llvm.org/show_bug.cgi?id=34129 (the lack of opt-viewer testing). It's also related to https://github.com/apple/swift/pull/12938 and the idea is to expose LLVM_HAVE_OPT_VIEWER_MODULES to the Swift cmake. Differential Revision: https://reviews.llvm.org/D40202 llvm-svn: 319073
* [opt-viewer] Fix option nameAdam Nemet2017-11-271-1/+1
| | | | llvm-svn: 319072
* [llvm-objcopy] Add --strip-all-gnu and change --strip-allJake Ehrlich2017-11-273-37/+82
| | | | | | | | | | | | | | GNU's --strip-all doesn't strip as aggressively as it could in general. Currently llvm-objcopy copies the exact behavoir of GNU's --strip-all. eu-strip is used as a drop in replacement for GNU strip/objcopy in many many places without issue. eu-strip removes non-allocated sections and keeps .gnu.warning* sections. Because --strip-all will likely be the most widely used stripping option we should make --strip-all as aggressive as it can safely be. Since we have evidence from eu-strip that this is a safe option we should allow it. For those that might still have an issue afterwards I've added --strip-all-gnu as an exact drop in replacement for GNU's --strip-all as well. llvm-svn: 319071
* [BinaryStream] Support growable streams.Zachary Turner2017-11-2710-39/+260
| | | | | | | | | The existing library assumed that a stream's length would never change. This makes some things simpler, but it's not flexible enough for what we need, especially for writable streams where what you really want is for each call to write to actually append. llvm-svn: 319070
* [cmake] Pass -Wl,-z,nodelete on Linux to prevent unloadingMichal Gorny2017-11-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Prevent unloading shared libraries on Linux when dlclose() is called. This is necessary since command-line option parsing API relies on registering the global option instances in the option parser instance which can be loaded in a different shared library. Given that we can't reliably remove those options when a library is unloaded, the parser ends up containing dangling references. Since glibc has relatively complex library unloading rules, some of the LLVM libraries can be unloaded while others (including the Support library) stay loaded causing quite a mayhem. To reliably prevent that, just forbid unloading all libraries -- it's a very bad idea anyway. While the issue arguably happens only with BUILD_SHARED_LIBS, it may affect any library reusing llvm::cl interface. Based on patch provided Ross Hayward on https://bugs.gentoo.org/617154. Previously hit by Fedora back in Feb 2016: https://lists.freedesktop.org/archives/mesa-dev/2016-February/107242.html Differential Revision: https://reviews.llvm.org/D40459 llvm-svn: 319069
* [X86] Remove an unused isel pattern that looked for pshufd with v4f32 type.Craig Topper2017-11-271-12/+0
| | | | | | I don't believe our current lowering/combining would ever produce such a node. We only produce integer typed pshufds. llvm-svn: 319068
* [InstCombine] use 'auto' with 'dyn_cast'; NFCSanjay Patel2017-11-271-3/+2
| | | | llvm-svn: 319067
* [X86] Teach combineX86ShuffleChain that AllowIntDomain requires at least SSE2.Craig Topper2017-11-271-1/+1
| | | | | | I don't have a good test case for this at the moment. I was playing around with a change in legalizing and triggered this code to produce a PSHUFD with sse1 only. llvm-svn: 319066
* [X86][AVX512] Tag AVX512 PACKSS/PACKUS/PMADDWD/PMADDUBSW instructions with ↵Simon Pilgrim2017-11-272-20/+29
| | | | | | | | SSE_PACK/SSE_PMADD schedule classes llvm-svn: 319065
* [Hexagon] Implement HexagonSubtarget::isHVXVectorTypeKrzysztof Parzyszek2017-11-272-27/+14
| | | | llvm-svn: 319064
* [X86] Add avx512bw command lines to vselect-packss.llCraig Topper2017-11-271-36/+109
| | | | | | This shows several places where we fail to use masked move or blendm. llvm-svn: 319063
* Delete obsolete function mergeUseListsImplJonas Hahnfeld2017-11-271-6/+0
| | | | | | | | mergeUseLists is implemented iteratively since r243590. Differential Revision: https://reviews.llvm.org/D40491 llvm-svn: 319061
* [X86] Make getSetCCResultType return vXi1 for any vXi32/vXi64 vector over ↵Craig Topper2017-11-273-803/+44
| | | | | | | | | | 512 bits long when AVX512 is enabled. Similar for vXi16/vXi8 with BWI. Any vector larger than 512 bits will be split to 512 bits during legalization. But without this we will fold sexts with them before that making it difficult to recover leading to scalarization. llvm-svn: 319059
* [X86][SSE] Fix roundpd instructions to correctly use IIC_SSE_ROUNDPD_* ↵Simon Pilgrim2017-11-271-2/+2
| | | | | | itineraries llvm-svn: 319054
* [AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodesDmitry Preobrazhensky2017-11-274-6/+91
| | | | | | | | | See bug 35433: https://bugs.llvm.org/show_bug.cgi?id=35433 Differential Revision: https://reviews.llvm.org/D40493 Reviewers: artem.tamazov, SamWot, arsenm llvm-svn: 319050
* [Power9] Improvements to vector extract with variable index exploitationZaara Syeda2017-11-272-25/+177
| | | | | | | | | | This patch extends on to rL307174 to not use the power9 vector extract with variable index instructions when extracting word element 1. For such cases, the existing selection of MFVSRWZ provides a better sequence. Differential Revision: https://reviews.llvm.org/D38287 llvm-svn: 319049
* [XRay] Fix typo in docs. NFCFangrui Song2017-11-272-4/+4
| | | | | | | | Reviewers: dberris Differential Revision: https://reviews.llvm.org/D40461 llvm-svn: 319047
* [X86][AVX512] Tag AVX512 sqrt instructions with SSE_SQRT schedule classesSimon Pilgrim2017-11-271-29/+32
| | | | llvm-svn: 319045
* [llvm-dwarfdump] Display DW_AT_high_pc as absolute valueJonas Devlieghere2017-11-275-17/+30
| | | | | | | | | | | | | | | | | | | | | | | | DWARF4 relative DW_AT_high_pc values are now displayed as absolute addresses. The relative value is only shown when explicitly dumping the forms, i.e. in show-form or verbose mode. ``` DW_AT_low_pc (0x0000000000000049) DW_AT_high_pc (0x00000019) ``` becomes ``` DW_AT_low_pc (0x0000000000000049) DW_AT_high_pc (0x0000000000000062) ``` Differential revision: https://reviews.llvm.org/D40317 rdar://35416943 llvm-svn: 319044
* [InstSimplify] use m_APFloat to simplify fcmp folds; NFCISanjay Patel2017-11-271-13/+7
| | | | llvm-svn: 319043
* [InstSimplify] add fcmp with negative constant tests; NFCSanjay Patel2017-11-271-0/+46
| | | | | | This is a superset of the tests proposed with D40012 to show another potential improvement. llvm-svn: 319041
* [DAG] Do MergeConsecutiveStores again before Instruction SelectionNirav Dave2017-11-2713-77/+79
| | | | | | | | | | | | | | | | Summary: Now that store-merge is only generates type-safe stores, do a second pass just before instruction selection to allow lowered intrinsics to be merged as well. Reviewers: jyknight, hfinkel, RKSimon, efriedma, rnk, jmolloy Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33675 llvm-svn: 319036
* [X86] Add INVLPGA to the existing INVLPG schedulingSimon Pilgrim2017-11-272-13/+14
| | | | llvm-svn: 319031
* [mips] fix asmstring of Ext and Ins instructions and mips16 JALRC/JRCPetar Jovanovic2017-11-273-5/+67
| | | | | | | | | | | | | | | Make the print format consistent with other assembler instructions. Adding a tab character instead of space in asmstring of Ext and Ins instructions. Removing space around the tab character for JALRC and replacing space with tab in JRC. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D38144 llvm-svn: 319030
* [X86] Add scheduling tests for invlpg/invlpgaSimon Pilgrim2017-11-271-0/+84
| | | | llvm-svn: 319029
* [Support] Fix locking of shared variable in threadpoolJan Korous2017-11-271-1/+1
| | | | llvm-svn: 319027
* [AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsicsVedran Miletic2017-11-276-0/+352
| | | | | | | | | | | | | | AMDGPU backend errors with "unsupported call to function" upon encountering a call to llvm.log{,10}.{f16,f32} intrinsics. This patch adds custom lowering to avoid that error on both R600 and SI. Reviewers: arsenm, jvesely Subscribers: tstellar Differential Revision: https://reviews.llvm.org/D29942 llvm-svn: 319025
* [CGP] Fix handling of null pointer values in optimizeMemoryInstJohn Brawn2017-11-272-9/+59
| | | | | | | | | | | The current way that trivial addressing modes are detected incorrectly thinks that null pointers are non-trivial, leading to an infinite loop where we keep duplicating the same select. Fix this by aware of null when deciding if an addressing mode is trivial. Differential Revision: https://reviews.llvm.org/D40447 llvm-svn: 319019
* [NFC] Add missing unit tests for EquivalenceClassesMax Kazantsev2017-11-273-0/+96
| | | | llvm-svn: 319018
* [X86][FMA] Tag all FMA/FMA4 instructions with WriteFMA schedule classSimon Pilgrim2017-11-2710-52/+75
| | | | | | | | | | As mentioned on PR17367, many instructions are missing scheduling tags preventing us from setting 'CompleteModel = 1' for better instruction analysis. This patch deals with FMA/FMA4 which is one of the bigger offenders (along with AVX512 in general). Annoyingly all scheduler models need to define WriteFMA (now that its actually used), even for older targets without FMA/FMA4 support, but that is an existing problem shared by other schedule classes. Differential Revision: https://reviews.llvm.org/D40351 llvm-svn: 319016
* [ARM] Fix an off-by-one error when restoring LR for 16-bit ThumbMomchil Velikov2017-11-274-7/+7
| | | | | | | | | | | | | | The commit https://reviews.llvm.org/rL318143 computes incorrectly to offset to restore LR from. The number of tPOP operands is 2 (condition) + 2 (implicit def and use of SP) + count of the popped registers. We need to load LR from just past the last register, hence the correct offset should be either getNumOperands() - 4 and getNumExplicitOperands() - 2 (multiplied by 4). Differential revision: https://reviews.llvm.org/D40305 llvm-svn: 319014
* Update BTVER2 sched numbers for SSE42 string instructions.Andrew V. Tischenko2017-11-272-32/+38
| | | | | | Differential Revision: https://reviews.llvm.org/D39846 llvm-svn: 319013
* [SelectionDAG] Teach SplitVecRes_SETCC to call GetSplitVector if the ↵Craig Topper2017-11-272-354/+337
| | | | | | operands have already been split. llvm-svn: 319010
* [SelectionDAG] Fix function name in comment. NFCCraig Topper2017-11-271-2/+2
| | | | llvm-svn: 319009
* [X86] Fix an assert that was incorrectly checking for BMI instead of AVX512VBMI.Craig Topper2017-11-261-2/+1
| | | | | | The check is actually unnecessary since AVX512VBMI implies AVX512BW which is the other part of the assert. llvm-svn: 319006
* [X86][3DNow] Add 3DNow! instruction itinerary and scheduling classesSimon Pilgrim2017-11-263-85/+132
| | | | llvm-svn: 319005
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