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* Initialize the RelocationSectionBase::Section member.James Y Knight2017-09-261-0/+2
| | | | | | In r314227, it wasn't always, and would thus contain random garbage. llvm-svn: 314256
* [Dominators] Invalidate DFS numbers upon edge deletionsJakub Kuderski2017-09-261-0/+2
| | | | | | | This patch makes DeleteEdge correctly invalidate DFS numbers in the incremental updater. This should fix PR34466 and related bugs. llvm-svn: 314254
* [BypassSlowDivision] Improve our handling of divisions by constantsSanjoy Das2017-09-262-7/+90
| | | | | | | | | | | | | | | Summary: Don't bail out on constant divisors for divisions that can be narrowed without introducing control flow . This gives us a 32 bit multiply instead of an emulated 64 bit multiply in the generated PTX assembly. Reviewers: jlebar Subscribers: jholewinski, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D38265 llvm-svn: 314253
* [AArch64][Falkor] Fix bug in falkor prefetcher fix pass.Geoff Berry2017-09-262-3/+33
| | | | | | | | | | | | | | | Summary: In rare cases, loads that don't get prefetched that were marked as strided loads could cause a crash if they occurred in a loop with other colliding loads. Reviewers: mcrosier Subscribers: aemerson, rengolin, javed.absar, kristof.beyls Differential Revision: https://reviews.llvm.org/D38261 llvm-svn: 314252
* [AArch64][Falkor] Fix correctness bug in falkor prefetcher fix pass and ↵Geoff Berry2017-09-262-60/+318
| | | | | | | | | | | | | | | | | | | | | correct some opcode tag computations. Summary: This addresses a correctness bug for LD[1234]*_POST opcodes that have the prefetcher fix applied to them: the base register was not being written back from the temp after being incremented, so it would appear to never be incremented. Also, fix some opcode tag computations based on some updated HW details to get better tag avoidance and thus better prefetcher performance. Reviewers: mcrosier Subscribers: aemerson, rengolin, javed.absar, kristof.beyls Differential Revision: https://reviews.llvm.org/D38256 llvm-svn: 314251
* [X86] Fix register class name in a comment. NFCCraig Topper2017-09-261-1/+1
| | | | llvm-svn: 314250
* Recommit r314151 "[X86] Make all the NOREX CodeGenOnly instructions into ↵Craig Topper2017-09-2612-60/+70
| | | | | | | | postRA pseudos like the NOREX version of TEST."" The late MOV8rr_NOREX that caused the crash has been removed. llvm-svn: 314249
* [X86] Don't emit X86::MOV8rr_NOREX from X86InstrInfo::copyPhysReg.Craig Topper2017-09-261-7/+5
| | | | | | This hook is called after register allocation with two physical registers. We don't need a separate instruction at that time to force register class constraints. I left in the assert though. We also have a fatal error in X86MCCodeEmitter if we ever encode an H-reg and a REX prefix. llvm-svn: 314248
* [X86] Fix typo in comment. NFCCraig Topper2017-09-261-1/+1
| | | | llvm-svn: 314247
* [WebAssembly] Model weakly defined symbols as wasm exportsSam Clegg2017-09-263-46/+42
| | | | | | | | | | | | | Previously these were being included as both imports and exports, with the import being satisfied by the export (or some strong symbol) at runtime. However proved unnecessary and actually complicated linking as it meant there was not a 1-to-1 mapping between a wasm function /global index and a linker symbol. Differential Revision: https://reviews.llvm.org/D38246 llvm-svn: 314245
* [PowerPC] Reverting sequence of patches for elimination of comparison ↵Nemanja Ivanovic2017-09-2689-1061/+88
| | | | | | | | | | | | | | | | | | | | | | instructions In the past while, I've committed a number of patches in the PowerPC back end aimed at eliminating comparison instructions. However, this causes some failures in proprietary source and these issues are not observed in SPEC or any open source packages I've been able to run. As a result, I'm pulling the entire series and will refactor it to: - Have a single entry point for easy control - Have fine-grained control over which patterns we transform A side-effect of this is that test cases for these patches (and modified by them) are XFAIL-ed. This is a temporary measure as it is counter-productive to remove/modify these test cases and then have to modify them again when the refactored patch is recommitted. The failure will be investigated in parallel to the refactoring effort and the recommit will either have a fix for it or will leave this transformation off by default until the problem is resolved. llvm-svn: 314244
* [X86][LLVM]Expanding Supports lowerInterleavedStore() in ↵Michael Zuckerman2017-09-263-182/+300
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | X86InterleavedAccess (VF{8|16|32} stride 3) This patch expands the support of lowerInterleavedStore to {8|16|32}x8i stride 3. LLVM creates suboptimal shuffle code-gen for AVX2. In overall, this patch is a specific fix for the pattern (Strid=3 VF={8|16|32}) . This patch is part two of two patches and it covers the store (interlevaed) side. The patch goal is to optimize the following sequence: a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 into a0 b0 c0 a1 b1 c1 a2 b2 c2 a3 b3 c3 a4 b4 c4 a5 b5 c5 a6 b6 c6 a7 b7 c7 Reviewers: zvi guyblank dorit Ayal Differential Revision: https://reviews.llvm.org/D37117 Change-Id: I56ced8bcbea809a37654060771911ade20246ccc llvm-svn: 314234
* [InstCombine] Remove one use restriction on the shift for calls to ↵Craig Topper2017-09-262-3/+22
| | | | | | | | | | | | foldICmpAndShift. If this transformation succeeds, we're going to remove our dependency on the shift by rewriting the and. So it doesn't matter how many uses the shift has. This distributes the one use check to other transforms in foldICmpAndConstConst that do need it. Differential Revision: https://reviews.llvm.org/D38206 llvm-svn: 314233
* [WebAssembly] Use function/global index space in WasmSymbolSam Clegg2017-09-262-16/+25
| | | | | | | | | | | | | | | | | | | It is useful for the symbol to contain the index of the function of global it represents in the function/global index space. For imports we also store the import index so that the linker can find, for example, the signature of the corresponding function, which is defined by the import In the long run we need to decide whether this API surface should be closer to binary (where imported functions are seperate) or the wasm spec (where the function index space is unified). Differential Revision: https://reviews.llvm.org/D38189 llvm-svn: 314230
* [llvm-objcopy] Add support for dynamic relocationsJake Ehrlich2017-09-264-40/+72
| | | | | | | | | | | | | | | This change adds support for dynamic relocations (allocated SHT_REL/SHT_RELA sections with a dynamic symbol table as their link). The binary I added for the test is here: https://drive.google.com/file/d/0B3gtIAmiMwZXSjJUZE9pUjd4M0k/view?usp=sharing Unless support for dynamic symbol tables in yaml2obj is added this is needed. Differential Revision: https://reviews.llvm.org/D37915 llvm-svn: 314227
* [NVPTX] added match.{any,all}.sync instructions, intrinsics & builtins.Artem Belevich2017-09-266-0/+237
| | | | | | Differential Revision: https://reviews.llvm.org/D38191 llvm-svn: 314223
* [mips] Use llvm-dwarfdump to simplify the test. NFCSimon Atanasyan2017-09-261-151/+42
| | | | llvm-svn: 314222
* [X86] Add support for v16i32 UMUL_LOHI/SMUL_LOHICraig Topper2017-09-263-729/+68
| | | | | | | | | | | | | | Summary: This patch extends the v8i32/v4i32 custom lowering to support v16i32 Reviewers: zvi, RKSimon Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38274 llvm-svn: 314221
* [Hexagon] Fix a typo: #ifndef DEBUG -> #ifndef NDEBUGKrzysztof Parzyszek2017-09-261-1/+1
| | | | llvm-svn: 314216
* [Hexagon] Fix initialization of HexagonSubtargetKrzysztof Parzyszek2017-09-262-38/+18
| | | | | | | Make sure that "initializeSubtargetDependencies" sets all members that InstrInfo and the like may depend on. llvm-svn: 314214
* [dwarfdump] Skip 'stripped' sectionsJonas Devlieghere2017-09-267-0/+39
| | | | | | | | | | | | | | | | | | | When dsymutil generates the companion file, its strips all unnecessary sections by omitting their body and setting the offset in their corresponding load command to zero. One such section is the .eh_frame section, as it contains runtime information rather than debug information and is part of the __TEXT segment. When reading this section, we would just read the number of bytes specified in the load command, starting from offset 0 (i.e. the beginning of the file). Rather than trying to parse this obviously invalid section, dwarfdump now skips this. Differential revision: https://reviews.llvm.org/D38135 llvm-svn: 314208
* [X86][XOP] Merge rotation opcodes with AVX512 equivalents. NFCI.Simon Pilgrim2017-09-265-26/+19
| | | | | | | | The XOP rotations act as ROTL with +ve values and ROTR with -ve values, which means that we can treat them all as ROTL with unsigned modulo. We already check that we're only trying to lower as ROTL for XOP rotations. Differential Revision: https://reviews.llvm.org/D37949 llvm-svn: 314207
* [DSE] Merge stores when the later store only writes to memory locations the ↵Sanjay Patel2017-09-265-5/+494
| | | | | | | | | | | | | | | | | | | | | | | | | | | early store also wrote to (2nd try) This is a 2nd attempt at: https://reviews.llvm.org/rL310055 ...which was reverted at rL310123 because of PR34074: https://bugs.llvm.org/show_bug.cgi?id=34074 In this version, we break out of the inner loop after we successfully merge and kill a pair of stores. In the earlier rev, we were continuing instead, which meant we could process the invalid info from a now dead store. Original commit message (authored by Filipe Cabecinhas): This fixes PR31777. If both stores' values are ConstantInt, we merge the two stores (shifting the smaller store appropriately) and replace the earlier (and larger) store with an updated constant. In the future we should also support vectors of integers. And maybe float/double if we can. Differential Revision: https://reviews.llvm.org/D30703 llvm-svn: 314206
* [x86] fix pr29061Coby Tayree2017-09-262-6/+52
| | | | | | | | | | https://bugs.llvm.org//show_bug.cgi?id=29061 Don't try referencing REX-needed regs when not on 64bit mode Aligns to GCC Differetial Revision: https://reviews.llvm.org/D37801 llvm-svn: 314203
* Tidyup P->getComplexPatternInfo call by moving it inside if( != NULL) test. ↵Simon Pilgrim2017-09-261-3/+1
| | | | | | NFCI. llvm-svn: 314202
* Don't move llvm.localescape outside the entry block in the GCOV profiling passSylvestre Ledru2017-09-261-1/+11
| | | | | | | | | | | | | | | | | Summary: This fixes https://bugs.llvm.org/show_bug.cgi?id=34714. Patch by Marco Castelluccio Reviewers: rnk Reviewed By: rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38224 llvm-svn: 314201
* Revert "[X86] Make all the NOREX CodeGenOnly instructions into postRA ↵Benjamin Kramer2017-09-2612-70/+60
| | | | | | | | pseudos like the NOREX version of TEST." Makes llc crash. This reverts commit r314151. llvm-svn: 314199
* [dsymutil] Better support for symbol aliasesJonas Devlieghere2017-09-265-0/+43
| | | | | | | | | | | This patch adds logic to follow a symbol's aliases when the symbol name cannot be found in the current object file. It checks the main binary for the symbol's address and queries the current object for its aliases (symbols with the same address) before printing out a warning. Differential revision: https://reviews.llvm.org/D38230 llvm-svn: 314198
* [X86] Finishing broadcastf32x2 and broadcasti32x2 intrinsics lowering to IR. ↵Uriel Korach2017-09-267-145/+114
| | | | | | | | | | | | llvm side. Removing X86 broadcast(f/i)32x2 intrinsics from llvm. Adding autoUpgrade support. Moving matching tests from avx512dq-intrinsics.ll to avx512dq-intrinsics-upgrade.ll and from avx512dqvl-intrinsics.ll to avx512dqvl-intrinsics-upgrade.ll. Differential Revision: https://reviews.llvm.org/D38220 llvm-svn: 314195
* CMake: Add option to set LLVM_ENABLE_DUMPMatthias Braun2017-09-262-0/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D38267 llvm-svn: 314186
* TargetLibraryInfo: Stop guessing wchar_t sizeMatthias Braun2017-09-266-16/+32
| | | | | | | | | | | | | | Usually the frontend communicates the size of wchar_t via metadata and we can optimize wcslen (and possibly other calls in the future). In cases without the wchar_size metadata we would previously try to guess the correct size based on the target triple; however this is fragile to keep up to date and may miss users manually changing the size via flags. Better be safe and stop guessing and optimizing if the frontend didn't communicate the size. Differential Revision: https://reviews.llvm.org/D38106 llvm-svn: 314185
* [AVR] Fix the build after setting alignment to 1 in r314179Dylan McKay2017-09-263-9/+9
| | | | | | Changing all types to be byte-aligned broke a small number of tests. llvm-svn: 314183
* [AVR] Prefer BasicBlock::getIterator over Function::begin()Dylan McKay2017-09-261-1/+1
| | | | | | Thanks to Eli Friedman for the suggestion. llvm-svn: 314182
* [AVR] When lowering shifts into loops, put newly generated MBBs in the sameDylan McKay2017-09-261-2/+4
| | | | | | | | | | | spot as the original MBB Discovered in avr-rust/rust#62 https://github.com/avr-rust/rust/issues/62 Patch by Gergo Erdi. llvm-svn: 314180
* [AVR] Use 1-byte alignment for all data typesDylan McKay2017-09-261-1/+1
| | | | | | | | | | | | | | This was an oversight in the original backend data layout. The AVR architecture does not have the concept of unaligned loads - all loads/stores from all addresses are aligned to one byte. Discovered in avr-rust issue #64 https://github.com/avr-rust/rust/issues/64 Patch By Gergo Erdi. llvm-svn: 314179
* [docs] llvm-cov: Make docs for boolean options more consistentVedant Kumar2017-09-251-8/+9
| | | | llvm-svn: 314176
* [llvm-cov] Warn if -show-functions is used without query filesVedant Kumar2017-09-252-2/+12
| | | | | | | | | | llvm-cov's report mode does not print any output when -show-functions is specified and no source files are specified. This can be surprising, so the tool should at least print out an error message when this happens. rdar://problem/34636859 llvm-svn: 314175
* Modernize commentsAdrian Prantl2017-09-251-13/+15
| | | | llvm-svn: 314174
* Modernize commentsAdrian Prantl2017-09-251-15/+16
| | | | llvm-svn: 314173
* Add section headers to SpecialCaseListsVlad Tsyrklevich2017-09-256-156/+296
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Sanitizer blacklist entries currently apply to all sanitizers--there is no way to specify that an entry should only apply to a specific sanitizer. This is important for Control Flow Integrity since there are several different CFI modes that can be enabled at once. For maximum security, CFI blacklist entries should be scoped to only the specific CFI mode(s) that entry applies to. Adding section headers to SpecialCaseLists allows users to specify more information about list entries, like sanitizer names or other metadata, like so: [section1] fun:*fun1* [section2|section3] fun:*fun23* The section headers are regular expressions. For backwards compatbility, blacklist entries entered before a section header are put into the '[*]' section so that blacklists without sections retain the same behavior. SpecialCaseList has been modified to also accept a section name when matching against the blacklist. It has also been modified so the follow-up change to clang can define a derived class that allows matching sections by SectionMask instead of by string. Reviewers: pcc, kcc, eugenis, vsk Reviewed By: eugenis, vsk Subscribers: vitalybuka, llvm-commits Differential Revision: https://reviews.llvm.org/D37924 llvm-svn: 314170
* Revert r312724 ("[ARM] Remove redundant vcvt patterns.").Eli Friedman2017-09-252-14/+28
| | | | | | | | | | | | | | It leads to some improvements, but also a regression for the simple case, so it's not clearly a good idea. test/CodeGen/ARM/vcvt.ll now has test coverage to show the difference. Ultimately, the right solution is probably to custom-lower fp-to-int conversions, to something like ARMISD::VCVT_F32_S32 plus a bitcast. It's hard to do the right thing when the implicit bitcast isn't visible to DAG transforms. llvm-svn: 314169
* [GlobalISel] Update the documentation and comment for G_[UN]MERGE_VALUESQuentin Colombet2017-09-252-0/+6
| | | | | | | | | In r296921, we added the G_[UN]MERGE_VALUES node, but did not update the documentation. Fixing that. NFC. llvm-svn: 314168
* [GlobalISel] Update the documentation for G_SEQUENCEQuentin Colombet2017-09-251-2/+0
| | | | | | | | This instruction has been removed in r306120. NFC. llvm-svn: 314167
* [GlobalISel] Update the documentation and comments for G_EXTRACTQuentin Colombet2017-09-252-3/+3
| | | | | | | | | In r297100, G_EXTRACT changed from a multiple results instruction to a single result one. Update the documentation accordingly. NFC. llvm-svn: 314166
* X86: remove R12 from CSR on Windows x64 SwiftCCSaleem Abdulrasool2017-09-253-22/+23
| | | | | | | | R12 is used for the SwiftError parameter. It is no longer a CSR as it is used for transfer the SwiftError, and the caller must preserve it if they need to. llvm-svn: 314165
* [ARM] Fix tests for vcvt+store to return void.Eli Friedman2017-09-251-8/+8
| | | | | | | This is what I meant to do in r314161; I didn't realize I'd messed up because the generated assembly is currently identical. llvm-svn: 314163
* [ARM] Add tests for vcvt followed by store.Eli Friedman2017-09-251-0/+52
| | | | llvm-svn: 314161
* [ARM] Regenerate vcvt test checks.Eli Friedman2017-09-251-50/+213
| | | | llvm-svn: 314160
* [InstCombine] Move an optimization from foldICmpAndConstConst to ↵Craig Topper2017-09-251-16/+10
| | | | | | | | | | foldICmpUsingKnownBits All this optimization cares about is knowing how many low bits of LHS is known to be zero and whether that means that the result is 0 or greater than the RHS constant. It doesn't matter where the zeros in the low bits came from. So we don't need to specifically look for an AND. Instead we can use known bits. Differential Revision: https://reviews.llvm.org/D38195 llvm-svn: 314153
* [X86] Don't select anyext GR32->GR64 to SUBREG_TO_REG. Use INSERT_SUBREG ↵Craig Topper2017-09-253-139/+139
| | | | | | | | | | | | instead. As far as I know SUBREG_TO_REG is stating that the upper bits are 0. But if we are just converting the GR32 with no checks, then we have no reason to say the upper bits are 0. I don't really know how to test this today since I can't find anything that looks that closely at SUBREG_TO_REG. The test changes here seems to be some perturbance of register allocation. Differential Revision: https://reviews.llvm.org/D38001 llvm-svn: 314152
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