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* GlobalISel: correctly translate invoke when callee is a register.Tim Northover2017-01-302-2/+20
| | | | | | This should fix the GlobalISel verifier. llvm-svn: 293550
* [AMDGPU] Internalize non-kernel symbolsStanislav Mekhanoshin2017-01-302-2/+68
| | | | | | | | | | | | | Since we have no call support and late linking we can produce code only for used symbols. This saves compilation time, size of the final executable, and size of any intermediate dumps. Run Internalize pass early in the opt pipeline followed by global DCE pass. To enable it RT can pass -amdgpu-internalize-symbols option. Differential Revision: https://reviews.llvm.org/D29214 llvm-svn: 293549
* Change the llvm-obdump(1) behavior with the -macho flag and inappropriate ↵Kevin Enderby2017-01-303-6/+12
| | | | | | | | | | | | | | | | | | file types. To better match the old darwin otool(1) behavior, when llvm-obdump(1) is used with the -macho option and the input file is not an object file simply print the file name and this message: foo: is not an object file and continue on to process other input files. Also in this case don’t exit non-zero. This should help in some OSS projects' with autoconf scripts that are expecting the old darwin otool(1) behavior. rdar://26828015 llvm-svn: 293547
* GlobalISel: account for differing exception selector sizes.Tim Northover2017-01-303-3/+14
| | | | | | | | | For some reason the exception selector register must be a pointer (that's assumed by SDag); on the other hand, it gets moved into an IR-level type which might be entirely different (i32 on AArch64). IRTranslator needs to be aware of this. llvm-svn: 293546
* GlobalISel: tidy up def/use test. NFC.Tim Northover2017-01-301-2/+2
| | | | llvm-svn: 293545
* LSR: Don't drop address space when type doesn't matchMatt Arsenault2017-01-302-4/+61
| | | | | | | | | | For targets with different addressing modes in each address space, if this is dropped querying isLegalAddressingMode later with this will give a nonsense result, breaking the isLegalUse assertions. This is a candidate for the 4.0 release branch. llvm-svn: 293542
* GlobalISel: translate memset & memmove.Tim Northover2017-01-303-10/+56
| | | | llvm-svn: 293541
* AMDGPU: Undo sub x, c -> add x, -c canonicalizationMatt Arsenault2017-01-306-2/+227
| | | | | | | | | This is worse if the original constant is an inline immediate. This should also be done for 64-bit adds, but requires fixing operand folding bugs first. llvm-svn: 293540
* [RDF] Add support for regmasksKrzysztof Parzyszek2017-01-304-79/+272
| | | | llvm-svn: 293538
* GlobalISel: permit unused vregs without a register-class after ISel.Tim Northover2017-01-302-5/+39
| | | | | | | This can happen if earlier combining has removed all uses of some VReg, which is fine and shouldn't flag an error. llvm-svn: 293537
* Fix the GCC build.Benjamin Kramer2017-01-302-30/+42
| | | | | | This is fairly ugly, but apparently GCC still doesn't understand C++11. llvm-svn: 293535
* Turn a TableGen FastISelEmitter warning into an error.Michael Kuperstein2017-01-301-7/+4
| | | | | | | | | | | | | Tablegen emitted a warning when the fast isel emitter created dead code by emitting a pattern that has no predicate before a pattern that has one. This should be an error but was originally only a warning because the X86 backend had a buggy definition that unintentionally caused this to be hit (PR21575). That has been fixed a while ago (r222094), so it's safe to upgrade the warning to an error. llvm-svn: 293534
* [X86][XOP] Fix test nameSimon Pilgrim2017-01-301-3/+3
| | | | llvm-svn: 293533
* Use SelectionDAG::getBuildVector helper function where possible. NFCI.Simon Pilgrim2017-01-302-21/+19
| | | | llvm-svn: 293532
* [IR] Remove global constructor from Function.cppBenjamin Kramer2017-01-301-2/+2
| | | | llvm-svn: 293528
* [MC] Remove global constructors from MCSectionMachO.cpp.Benjamin Kramer2017-01-301-12/+12
| | | | llvm-svn: 293526
* AMDGPU: Run AMDGPUCodeGenPrepare after inliningMatt Arsenault2017-01-301-9/+9
| | | | | | | With leaf functions, this makes nonsensical decisions based on the uniformity of the arguments. llvm-svn: 293525
* [InstCombine] enable (X >>?exact C1) << C2 --> X >>?exact (C1-C2) for ↵Sanjay Patel2017-01-302-28/+24
| | | | | | vectors with splat constants llvm-svn: 293524
* SDAG: Update ChainNodesMatched during UpdateChains if a node is replacedJustin Bogner2017-01-303-2/+51
| | | | | | | | | | | Previously, we would hit UB (or the ISD::DELETED_NODE assert) if we happened to replace a node during UpdateChains, because it would be left in the list we were iterating over. This nulls out the pointer when that happens so that we can avoid the issue. Fixes llvm.org/PR31710 llvm-svn: 293522
* Use SelectionDAG::getBuildVector/getSplatBuildVector helper functions where ↵Simon Pilgrim2017-01-301-7/+3
| | | | | | possible. NFCI. llvm-svn: 293520
* [InstCombine] add vector splat tests for (X >>?exact C1) << C2 --> X ↵Sanjay Patel2017-01-301-6/+36
| | | | | | >>?exact (C1-C2); NFC llvm-svn: 293517
* [libFuzzer] Implement TmpDir() for Windows.Marcos Pividori2017-01-301-1/+11
| | | | | | Differential Revision: https://reviews.llvm.org/D28977 llvm-svn: 293516
* NewGVN: Instead of changeToUnreachable, insert an instruction SimplifyCFG ↵Daniel Berlin2017-01-303-4/+7
| | | | | | will turn into unreachable when it runs llvm-svn: 293515
* AMDGPU: Make i32 uaddo/usubo legalMatt Arsenault2017-01-304-58/+195
| | | | llvm-svn: 293514
* DAG: Fold fneg into compare with constant into the constantMatt Arsenault2017-01-304-6/+273
| | | | | | | | fcmp (fneg x), c, pred -> fcmp x, -c, (swap pred) InstCombine already does this. llvm-svn: 293512
* [Orc] Add missing include.Benjamin Kramer2017-01-301-0/+1
| | | | llvm-svn: 293511
* [RDF] Extract the physical register information into a separate classKrzysztof Parzyszek2017-01-307-254/+344
| | | | llvm-svn: 293510
* Revert "AMDGPU/GlobalISel: Add support for simple shaders"Tom Stellard2017-01-3022-1496/+10
| | | | | | | | This reverts commit r293503. Revert while I investigate some of the buildbot failures. llvm-svn: 293509
* [InstCombine] use auto with obvious type; NFCSanjay Patel2017-01-301-3/+3
| | | | llvm-svn: 293508
* [InstCombine] enable (X <<nsw C1) >>s C2 --> X <<nsw (C1-C2) for vectors ↵Sanjay Patel2017-01-302-23/+19
| | | | | | with splat constants llvm-svn: 293507
* unique_ptrify some containers in GlobalISel::RegisterBankInfoDavid Blaikie2017-01-302-23/+13
| | | | | | | | | To simplify/clarify memory ownership, make leaks (as one was found/fixed recently) harder to write, etc. (also, while I was there - removed a duplicate lookup in a container) llvm-svn: 293506
* AMDGPU: Fix atomic_inc/atomic_dec + ds_swizzle not being divergentMatt Arsenault2017-01-303-0/+46
| | | | llvm-svn: 293504
* AMDGPU/GlobalISel: Add support for simple shadersTom Stellard2017-01-3022-10/+1496
| | | | | | | | | | | | Summary: We can select constant/global G_LOAD, global G_STORE, and G_GEP. Reviewers: qcolombet, MatzeB, t.p.northover, ab, arsenm Subscribers: mehdi_amini, vkalintiris, kzhuravl, wdng, nhaehnle, mgorny, yaxunl, tony-tye, modocache, llvm-commits, dberris Differential Revision: https://reviews.llvm.org/D26730 llvm-svn: 293503
* Update pr31758.ll for unreachable revertDaniel Berlin2017-01-301-1/+1
| | | | llvm-svn: 293502
* Revert "NewGVN: Make unreachable blocks be marked with unreachable"Daniel Berlin2017-01-303-33/+38
| | | | | | | | | This reverts commit r293196 Besides making things look nicer, ATM, we'd like to preserve analysis more than we'd like to destroy the CFG. We'll probably revisit in the future llvm-svn: 293501
* [X86][SSE] Add support for combining PINSRW+ASSERTZEXT+PEXTRW patterns with ↵Simon Pilgrim2017-01-302-15/+21
| | | | | | target shuffles llvm-svn: 293500
* DAG: Constant fold fp16_to_fp/fp16_to_fpMatt Arsenault2017-01-3014-163/+142
| | | | | | | This fixes emitting conversions of constants on targets without legal f16 that need to use these for legalization. llvm-svn: 293499
* [InstCombine] fixed to propagate 'exact' on lshrSanjay Patel2017-01-302-2/+2
| | | | | | | | | | | | | | | | | The original shift is bigger, so this may qualify as 'obvious', but here's an attempt at an Alive-based proof: Name: exact Pre: (C1 u< C2) %a = shl i8 %x, C1 %b = lshr exact i8 %a, C2 => %c = lshr exact i8 %x, C2 - C1 %b = and i8 %c, ((1 << width(C1)) - 1) u>> C2 Optimization is correct! llvm-svn: 293498
* [InstCombine] add 'exact' to lshr to show that it got dropped; NFC Sanjay Patel2017-01-301-1/+2
| | | | llvm-svn: 293496
* [Coroutines] Add header guard to header that's missing one.Benjamin Kramer2017-01-301-0/+5
| | | | llvm-svn: 293494
* [Inliner] Fold analysis remarks into missed remarksAdam Nemet2017-01-303-19/+14
| | | | | | This significantly reduces the noise level of these messages. llvm-svn: 293492
* [RDF] Add phis for entry block live-ins (in addition to function live-ins)Krzysztof Parzyszek2017-01-303-14/+22
| | | | llvm-svn: 293491
* [Inliner] Fix a comment to match the code. NFC.Haicheng Wu2017-01-301-2/+2
| | | | | | | | TotalAltCost => TotalSecondaryCost Differential Revision: https://reviews.llvm.org/D29231 llvm-svn: 293490
* [InstCombine] enable lshr(shl X, C1), C2 folds for vectors with splat constantsSanjay Patel2017-01-302-29/+28
| | | | llvm-svn: 293489
* [InstCombine] add tests for shift-shift patterns; NFCSanjay Patel2017-01-301-0/+57
| | | | llvm-svn: 293487
* Bring back r293480. It is safe now.Rafael Espindola2017-01-301-10/+10
| | | | | | | | | | | | | | | Original message: Fix the values of two xcore ELF flags. The values in llvm grew from a pre-MC day when they would not show up in .o files and are outside of the SHF_MASKPROC. Fortunately the MC output is not currently used as xcore has its own assemble and that assembler uses valid values. This updates llvm to use the same values as the xmos assembler. llvm-svn: 293486
* Only print architecture dependent flags for that architecture.Rafael Espindola2017-01-309-15/+27
| | | | | | | | | | Different architectures can have different meaning for flags in the SHF_MASKPROC mask, so we should always check what the architecture use before checking the flag. NFC for now, but will allow fixing the value of an xmos flag. llvm-svn: 293484
* TableGen: Fix infinite recursion in RegisterBankEmitterTom Stellard2017-01-302-3/+26
| | | | | | | | | | | | | | | | Summary: AMDGPU has two register classes with the same set of registers, and this was causing this tablegen backend would get stuck in infinite recursion. Reviewers: dsanders Reviewed By: dsanders Subscribers: tpr, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D29049 llvm-svn: 293483
* [Hexagon] Make header self-contained.Benjamin Kramer2017-01-301-0/+3
| | | | llvm-svn: 293482
* Revert "Fix the values of two xcore ELF flags."Rafael Espindola2017-01-301-10/+10
| | | | | | | | This reverts commit r293480. The patch is correct, but found bugs in other areas that need to be fixed. llvm-svn: 293481
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