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* Previous commit message should refer to 104308.Dale Johannesen2010-05-211-1/+1
| | | | llvm-svn: 104337
* Fix two bugs in 104348:Dale Johannesen2010-05-211-3/+9
| | | | | | | Case where MMX is disabled wasn't handled right. MMX->MMX bitconverts are Legal. llvm-svn: 104336
* added an assertion to MCObjectWriter::WriteBytes to catch misuse of the ↵Nathan Jeffords2010-05-211-0/+2
| | | | | | | | ZeroFillSize parameter If the size of the string is greater than the zero fill size, the function will attempt to write a very large string of zeros to the object file (~4GB on 32 bit platforms). This assertion will catch the scenario and crash the program before the write occurs. llvm-svn: 104334
* now that fp reg kill insertion stuff happens as a separateChris Lattner2010-05-212-38/+58
| | | | | | | | | | | | | | | | | | pass after isel instead of being interlaced with it, we can trust that all the code for a function has been isel'd before it is run. The practical impact of this is that we can scan for machine instr phis instead of doing a fuzzy match on the LLVM BB for phi nodes. Doing the fuzzy match required knowing when isel would produce an fp reg stack phi which was gross. It was also wrong in cases where select got lowered to a branch tree because cmovs aren't available (PR6828). Just do the scan on machine phis which is simpler, faster and more correct. This fixes PR6828. llvm-svn: 104333
* Use less evil form of switch stmt.Chris Lattner2010-05-211-2/+4
| | | | llvm-svn: 104331
* use continue to reduce nesting.Chris Lattner2010-05-211-14/+17
| | | | llvm-svn: 104330
* pull a nested loop of this pass out to its own function,Chris Lattner2010-05-211-42/+55
| | | | | | eliminating the gymnastics around the ContainsFPCode var. llvm-svn: 104328
* modernize this pass a bit, fit in 80 columns.Chris Lattner2010-05-211-6/+9
| | | | llvm-svn: 104326
* constify accessor.Chris Lattner2010-05-212-2/+3
| | | | llvm-svn: 104325
* Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a ↵Jakob Stoklund Olesen2010-05-213-34/+58
| | | | | | | | register is read." This reverts r104322. I think it was causing miscompilations. llvm-svn: 104323
* Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.Jakob Stoklund Olesen2010-05-213-58/+34
| | | | | | This correctly handles partial redefines and undef uses. llvm-svn: 104322
* Teach VirtRegRewriter to handle spilling in instructions that have multipleJakob Stoklund Olesen2010-05-212-1/+52
| | | | | | | | | | | | | definitions of the virtual register. This happens when spilling the registers produced by REG_SEQUENCE: %reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0 The rewriter would spill the register multiple times, dead store elimination tried to keep up, but ended up cutting the branch it was sitting on. llvm-svn: 104321
* If the first definition of a virtual register is a partial redef, add anJakob Stoklund Olesen2010-05-213-7/+24
| | | | | | | <imp-def> operand for the full register. This ensures that the full physical register is marked live after register allocation. llvm-svn: 104320
* Currently, createMachOStreamer() is invoked directly in llvm-mc whichMatt Fleming2010-05-213-1/+68
| | | | | | | | | isn't ideal if we want to be able to use another object file format. Add a createObjectStreamer() factory method so that the correct object file streamer can be instantiated for a given target triple. llvm-svn: 104318
* Split out the x86_32 an x86_64 ELF backends as they handle ELFMatt Fleming2010-05-211-2/+14
| | | | | | differently. This will make adding ELF support easier in the long run. llvm-svn: 104317
* Add support for parsing the ELF .type assembler directive.Matt Fleming2010-05-214-1/+52
| | | | llvm-svn: 104316
* Removed scaleNumbering method declaration from LiveInterval (not defined, ↵Lang Hames2010-05-211-4/+0
| | | | | | not used). llvm-svn: 104311
* Fix i64->f64 conversion, x86-64, -no-sse. A bitDale Johannesen2010-05-213-0/+45
| | | | | | | tricky since there's a 3rd 64-bit type, MMX vectors. PR 7135. llvm-svn: 104308
* Change ARM scheduling default to list-hybrid if the target supports floating ↵Evan Cheng2010-05-219-15/+18
| | | | | | point instructions (and is not using soft float). llvm-svn: 104307
* Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.Evan Cheng2010-05-211-1/+1
| | | | llvm-svn: 104306
* Remove dead option.Daniel Dunbar2010-05-211-3/+0
| | | | llvm-svn: 104303
* Simplify.Devang Patel2010-05-211-16/+8
| | | | llvm-svn: 104302
* Fix __crashreport_info__ declaration.Daniel Dunbar2010-05-201-2/+2
| | | | llvm-svn: 104300
* Allow targets more controls on what nodes are scheduled by reg pressure, ↵Evan Cheng2010-05-208-16/+52
| | | | | | what for latency in hybrid mode. llvm-svn: 104293
* DominatorTree.getNode can return null for unreachable blocks.Dan Gohman2010-05-201-1/+1
| | | | llvm-svn: 104290
* Minor code cleanups.Dan Gohman2010-05-201-8/+7
| | | | llvm-svn: 104287
* Print a space after the colon.Mikhail Glushenkov2010-05-201-2/+2
| | | | llvm-svn: 104279
* Make Solve check its own post-condition, to reduce clutter in theDan Gohman2010-05-201-1/+2
| | | | | | top-level LSRInstance logic. llvm-svn: 104278
* Add comments.Dan Gohman2010-05-201-0/+16
| | | | llvm-svn: 104276
* MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with ↵Daniel Dunbar2010-05-202-0/+27
| | | | | | movq. llvm-svn: 104275
* Rename variable. add comment.Devang Patel2010-05-202-3/+6
| | | | llvm-svn: 104274
* More code cleanups. Use iterators instead of indices when indicesDan Gohman2010-05-201-22/+24
| | | | | | aren't needed. llvm-svn: 104273
* X86: Model i64i32imm properly, as a subclass of all immediates.Daniel Dunbar2010-05-203-2/+29
| | | | llvm-svn: 104272
* X86: Fix immediate type of FOO64i32 operations.Daniel Dunbar2010-05-201-10/+10
| | | | llvm-svn: 104271
* tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honorDaniel Dunbar2010-05-202-0/+7
| | | | | | it. llvm-svn: 104270
* Fix OptimizeShadowIV to set Changed. Change OptimizeLoopTermCond to setDan Gohman2010-05-201-8/+7
| | | | | | | | | Changed directly instead of using a return value. Rename FilterOutUndesirableDedicatedRegisters's Changed variable to distinguish it from LSRInstance's Changed member. llvm-svn: 104269
* Add some comments.Dan Gohman2010-05-201-0/+6
| | | | llvm-svn: 104268
* Simplify this code. Don't do a DomTreeNode lookup for each visited block.Dan Gohman2010-05-201-14/+5
| | | | llvm-svn: 104267
* Refactor.Devang Patel2010-05-202-37/+76
| | | | llvm-svn: 104265
* Grammar fix. This is a test commit.Matt Fleming2010-05-201-1/+1
| | | | llvm-svn: 104264
* Minor code cleanups.Dan Gohman2010-05-201-20/+11
| | | | llvm-svn: 104263
* When canonicalizing icmp operand order to put the loop invariantDan Gohman2010-05-203-230/+257
| | | | | | | | | | | | operand on the left, the interesting operand is on the right. This fixes a bug where LSR was failing to recognize ICmpZero uses, which led it to be unable to reverse the induction variable in the attached testcase. Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test is extremely fragile and hard to meaningfully update. llvm-svn: 104262
* llvmc: Make segfault detection work on Win32.Mikhail Glushenkov2010-05-201-21/+28
| | | | llvm-svn: 104261
* Set Changed to true when canonicalizing ICmp operand order; even thoughDan Gohman2010-05-201-0/+1
| | | | | | it isn't a very interesting change, it's a change nonetheless. llvm-svn: 104260
* Handle Neon v2f64 and v2i64 vector shuffles as register copies.Bob Wilson2010-05-202-0/+25
| | | | | | This fixes the remaining issue with pr7167. llvm-svn: 104257
* Remove dbg_value workaround and associated command line optionJim Grosbach2010-05-201-20/+0
| | | | llvm-svn: 104254
* Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn'tDan Gohman2010-05-201-3/+0
| | | | | | have a pattern and it had an invalid encoding. llvm-svn: 104244
* The PPC MFCR instruction implicitly uses all 8 of the CRDale Johannesen2010-05-205-21/+24
| | | | | | | | | | | | | | registers. Currently it is not so marked, which leads to VCMPEQ instructions that feed into it getting deleted. If it is so marked, local RA complains about this sequence: vreg = MCRF CR0 MFCR <kill of whatever preg got assigned to vreg> All current uses of this instruction are only interested in one of the 8 CR registers, so redefine MFCR to be a normal unary instruction with a CR input (which is emitted only as a comment). That avoids all problems. 7739628. llvm-svn: 104238
* Strip llvm.dbg.lv also.Devang Patel2010-05-201-0/+6
| | | | llvm-svn: 104236
* Rename a variable to avoid shadowing.Dan Gohman2010-05-201-2/+3
| | | | llvm-svn: 104234
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