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* GlobalISel: support selection of extend operations.Tim Northover2016-10-112-0/+203
| | | | | | Patch mostly by Ahmed Bougaca. llvm-svn: 283937
* MIRParser: allow types on registers with a RegBank.Tim Northover2016-10-111-1/+2
| | | | | | This fixes some GlobalISel regression tests. llvm-svn: 283936
* Re-apply "Disallow ArrayRef assignment from temporaries."Jordan Rose2016-10-112-0/+44
| | | | | | | | | | This re-applies r283798, disabled in r283803, with the static_assert tests disabled under MSVC. The deleted functions still seem to catch mistakes in MSVC, so it's not a significant loss. Part of rdar://problem/16375365 llvm-svn: 283935
* Codegen: Tail-duplicate during placement.Kyle Butt2016-10-1125-95/+952
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tail duplication pass uses an assumed layout when making duplication decisions. This is fine, but passes up duplication opportunities that may arise when blocks are outlined. Because we want the updated CFG to affect subsequent placement decisions, this change must occur during placement. In order to achieve this goal, TailDuplicationPass is split into a utility class, TailDuplicator, and the pass itself. The pass delegates nearly everything to the TailDuplicator object, except for looping over the blocks in a function. This allows the same code to be used for tail duplication in both places. This change, in concert with outlining optional branches, allows triangle shaped code to perform much better, esepecially when the taken/untaken branches are correlated, as it creates a second spine when the tests are small enough. Issue from previous rollback fixed, and a new test was added for that case as well. Issue was worklist/scheduling/taildup issue in layout. Issue from 2nd rollback fixed, with 2 additional tests. Issue was tail merging/loop info/tail-duplication causing issue with loops that share a header block. Issue with early tail-duplication of blocks that branch to a fallthrough predecessor fixed with test case: tail-dup-branch-to-fallthrough.ll Differential revision: https://reviews.llvm.org/D18226 llvm-svn: 283934
* [x86] add tests for negate boolSanjay Patel2016-10-111-0/+101
| | | | llvm-svn: 283930
* Avoid braced initialization for default member initializers for MSVC 2013Reid Kleckner2016-10-112-3/+2
| | | | llvm-svn: 283928
* Silence -Wunused-but-set-variable warningArnold Schwaighofer2016-10-111-0/+1
| | | | llvm-svn: 283927
* Re-submit r283823: Define DbiStreamBuilder::addDbgStream to add stream.Rui Ueyama2016-10-113-2/+42
| | | | | | | The previous commit was failing because we filled empty slots of the debug stream index with kInvalidStreamIndex. It should've been 0. llvm-svn: 283925
* [sanitizer-coverage] use private linkage for coverage guards, delete old ↵Kostya Serebryany2016-10-112-13/+5
| | | | | | commented-out code. llvm-svn: 283924
* Fix build error on LP64 platforms.Rui Ueyama2016-10-111-1/+2
| | | | llvm-svn: 283922
* [raw_ostream] Raise some helper functions out of raw_ostream.Zachary Turner2016-10-114-137/+231
| | | | | | | | | | Low level functionality to format numbers were embedded in the implementation of raw_ostream. I have need to use these through an interface other than the overloaded stream operators, so they need to be raised to a level that they can be used from either raw_ostream operators or other code. llvm-svn: 283921
* [AMDGPU] Refactor waitcnt encodingKonstantin Zhuravlyov2016-10-115-66/+171
| | | | | | | | | | | | | - Refactor bit packing/unpacking - Calculate bit mask given bit shift and bit width - Introduce function for decoding bits of waitcnt - Introduce function for encoding bits of waitcnt - Introduce function for getting waitcnt mask (instead of using bare numbers) - Introduce function fot getting max waitcnt(s) (instead of using bare numbers) Differential Revision: https://reviews.llvm.org/D25298 llvm-svn: 283919
* Allow Switch instruction to have extractProfTotalWeight called as it can ↵Dehao Chen2016-10-111-1/+2
| | | | | | terminate a basic block. (NFC) llvm-svn: 283918
* Avoid unnecessary constexpr to appease MSVC 2013Reid Kleckner2016-10-111-1/+1
| | | | llvm-svn: 283916
* Fix "static initialization order fiasco" for the XCore Target.Mehdi Amini2016-10-116-15/+19
| | | | | | | | I fixed all the other Targets in r283702, and interestingly the sanitizers are only now "sometimes" catching this bug on the only one I missed. llvm-svn: 283914
* [Support] Fix undefined behavior in RandomNumberGenerator.Zachary Turner2016-10-111-4/+4
| | | | | | | | | This has existed pretty much forever AFAICT, but the code was never being exercised because nobody was using the class. A user of this class surfaced, and now we're breaking with UB. The code was obviously wrong, so it's fixed here. llvm-svn: 283912
* [AMDGPU] Fix test that was broken by rL283893Konstantin Zhuravlyov2016-10-111-1/+3
| | | | llvm-svn: 283911
* ARMMachineFunctionInfo.cpp: Add an initializer of ↵NAKAMURA Takumi2016-10-111-2/+2
| | | | | | | | ARMFunctionInfo::ReturnRegsCount in the explicit ctor. It caused crash since r283867. llvm-svn: 283909
* Reformat.NAKAMURA Takumi2016-10-111-4/+4
| | | | llvm-svn: 283908
* [DAG] add fold for masked negated sign-extended boolSanjay Patel2016-10-112-14/+12
| | | | | | | This enhances the fold added with: https://reviews.llvm.org/rL283900 llvm-svn: 283905
* [x86] add sext variants of tests added with r283894Sanjay Patel2016-10-111-6/+51
| | | | llvm-svn: 283903
* Let test pass for builds that support X86, but do not default to itBernard Ogden2016-10-111-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D25471 llvm-svn: 283902
* Fix test on non-x86 hostsBernard Ogden2016-10-111-1/+1
| | | | | | | | | | Summary: This test is allowed to run on non-x86 hosts and thus must use llvm-nm rather than nm. Differential Revision: https://reviews.llvm.org/D25473 llvm-svn: 283901
* [DAG] add fold for masked negated extended boolSanjay Patel2016-10-112-11/+16
| | | | | | | | | | | | | | The non-obvious motivation for adding this fold (which already happens in InstCombine) is that we want to canonicalize IR towards select instructions and canonicalize DAG nodes towards boolean math. So we need to recreate some folds in the DAG to handle that change in direction. An interesting implementation difference for cases like this is that InstCombine generally works top-down while the DAG goes bottom-up. That means we need to detect different patterns. In this case, the SimplifyDemandedBits fold prevents us from performing a zext to sext fold that would then be recognized as a negation of a sext. llvm-svn: 283900
* Silence unused warning in non-assert builds.Daniel Jasper2016-10-111-0/+1
| | | | llvm-svn: 283899
* [opt-viewer] Remove unnecessary call to demangleAdam Nemet2016-10-111-1/+1
| | | | llvm-svn: 283898
* [opt-viewer] Print hotness as percentage of the maximum hotnessAdam Nemet2016-10-111-2/+9
| | | | llvm-svn: 283897
* [opt-viewer] Convert another HTML output to use a multiline stringAdam Nemet2016-10-111-10/+16
| | | | llvm-svn: 283896
* [x86] add tests to show missed folds for masked boolsSanjay Patel2016-10-111-0/+48
| | | | llvm-svn: 283894
* AMDGPU/SI: Update ISA version numbers for Tonga and Polaris10/11.Changpeng Fang2016-10-115-7/+16
| | | | | | | | | | Differential Revision: http://reviews.llvm.org/D25454 Reviewers: tstellarAMD llvm-svn: 283893
* [cl] Don't print subcommand help when no subcommands present.Zachary Turner2016-10-111-4/+6
| | | | | | | | | | | | | | | | Previously we would print USAGE: <exe> [subcommand] [options] Even if no subcommands were present. This changes the output format to only print "[subcommand]" if there is at least one subcommand. Fixes llvm.org/pr30598 Patch by Serge Guelton llvm-svn: 283892
* [DAG] simplify logic; NFCSanjay Patel2016-10-111-8/+6
| | | | llvm-svn: 283885
* [DAG] hoist DL(N) and fix formatting; NFCSanjay Patel2016-10-111-25/+32
| | | | llvm-svn: 283884
* [X86][SSE] Regenerate scalar i64 uitofp testSimon Pilgrim2016-10-111-16/+41
| | | | | | Added 32-bit target test llvm-svn: 283883
* [X86][SSE] Regenerate vector load-trunc testSimon Pilgrim2016-10-111-1/+20
| | | | llvm-svn: 283881
* [X86][SSE] Regenerate vsplit and testsSimon Pilgrim2016-10-111-6/+53
| | | | | | To make it more obvious how bad some of that truncation code is.... llvm-svn: 283880
* [DAG] fix formatting; NFCSanjay Patel2016-10-111-72/+68
| | | | llvm-svn: 283878
* [LCSSA] Implement linear algorithm for the isRecursivelyLCSSAFormIgor Laevsky2016-10-115-40/+50
| | | | | | | | For each block check that it doesn't have any uses outside of it's innermost loop. Differential Revision: https://reviews.llvm.org/D25364 llvm-svn: 283877
* [x86] update test to use FileCheck and auto-generate checksSanjay Patel2016-10-111-5/+15
| | | | llvm-svn: 283876
* [Support/ELF] - Add OpenBSD PT_OPENBSD_RANDOMIZE, PT_OPENBSD_WXNEEDED constants.George Rimar2016-10-111-0/+3
| | | | | | | | Docs for reference: http://man.openbsd.org/OpenBSD-current/man5/elf.5 https://github.com/openbsd/src/commit/2a5a8fc7e30928c2cff57cfe5fb491c90d8478ad llvm-svn: 283872
* [Thumb] Save/restore high registers in Thumb1 pro/epiloguesOliver Stannard2016-10-116-36/+620
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The high registers are not allocatable in Thumb1 functions, but they could still be used by inline assembly, so we need to save and restore the callee-saved high registers (r8-r11) in the prologue and epilogue. This is complicated by the fact that the Thumb1 push and pop instructions cannot access these registers. Therefore, we have to move them down into low registers before pushing, and move them back after popping into low registers. In most functions, we will have low registers that are also being pushed/popped, which we can use as the temporary registers for saving/restoring the high registers. However, this is not guaranteed, so we may need to push some extra low registers to ensure that the high registers can be saved/restored. For correctness, it would be sufficient to use just one low register, but if we have enough low registers available then we only need one push/pop instruction, rather than one per high register. We can also use the argument/return registers when they are not live, and the link register when saving (but not restoring), reducing the number of extra registers we need to push. There are still a few extreme edge cases where we need two push/pop instructions, because not enough low registers can be made live in the prologue or epilogue. In addition to the regression tests included here, I've also tested this using a script to generate functions which clobber different combinations of registers, have different numbers of argument and return registers (including variadic arguments), allocate different fixed sized objects on the stack, and do or don't use variable sized allocas and the __builtin_return_address intrinsic (all of which affect the available registers in the prologue and epilogue). I ran these functions in a test harness which verifies that all of the callee-saved registers are correctly preserved. Differential Revision: https://reviews.llvm.org/D24228 llvm-svn: 283867
* [ARM] Fix registers clobbered by SjLj EH on soft-float targetsOliver Stannard2016-10-115-8/+39
| | | | | | | | | | | | | | | | | | | Currently, the Int_eh_sjlj_dispatchsetup intrinsic is marked as clobbering all registers, including floating-point registers that may not be present on the target. This is technically true, as we could get linked against code that does use the FP registers, but that will not actually work, as the soft-float code cannot save and restore the FP registers. SjLj exception handling can only work correctly if either all or none of the code is built for a target with FP registers. Therefore, we can assume that, when Int_eh_sjlj_dispatchsetup is compiled for a soft-float target, it is only going to be linked against other soft-float code, and so only clobbers the general-purpose registers. This allows us to check that no non-savable registers are clobbered when generating the prologue/epilogue. Differential Revision: https://reviews.llvm.org/D25180 llvm-svn: 283866
* [AArch64] Allow label arithmetic with add/sub/cmpDiana Picus2016-10-118-26/+345
| | | | | | | | | | | | | Allow instructions such as 'cmp w0, #(end - start)' by folding the expression into a constant. For ELF, we fold only if the symbols are in the same section. For MachO, we fold if the expression contains only symbols that are not linker visible. Fixes https://llvm.org/bugs/show_bug.cgi?id=18920 Differential Revision: https://reviews.llvm.org/D23834 llvm-svn: 283862
* Fix formatting in findRegisterUseOperandIdx. NFC.Fraser Cormack2016-10-111-7/+5
| | | | llvm-svn: 283860
* Reverted r283740 [Object/ELF] - Do not crash on invalid Header->e_shoff value.George Rimar2016-10-113-6/+0
| | | | | | | | | | | | | | | | Bot does not like it: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/17075 /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/test/Object/invalid.test:70:32: error: expected string not found in input INVALID-SEC-ADDRESS-ALIGNMENT: Invalid address alignment of section headers ^ <stdin>:1:1: note: scanning from here /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/include/llvm/Object/ELF.h:412:7: runtime error: upcast of misaligned address 0x000002d8b899 for type 'llvm::object::Elf_Shdr_Impl<llvm::object::ELFType<llvm::support::endianness::little, true> >', which requires 2 byte alignment ^ <stdin>:1:125: note: possible intended match here /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/include/llvm/Object/ELF.h:412:7: runtime error: upcast of misaligned address 0x000002d8b899 for type 'llvm::object::Elf_Shdr_Impl<llvm::object::ELFType<llvm::support::endianness::little, true> >', which requires 2 byte alignment llvm-svn: 283858
* Revert "Codegen: Tail-duplicate during placement."Daniel Jasper2016-10-1125-953/+95
| | | | | | | | | This reverts commit r283842. test/CodeGen/X86/tail-dup-repeat.ll causes and llc crash with our internal testing. I'll share a link with you. llvm-svn: 283857
* Use LLVM_CONSTEXPR to appease MSVC2013 (fixup for r283854)Mehdi Amini2016-10-111-2/+2
| | | | llvm-svn: 283855
* Make RandomNumberGenerator compatible with <random>Mehdi Amini2016-10-113-7/+41
| | | | | | | | | | | | | LLVM's RandomNumberGenerator wasn't compatible with the random distribution from <random>. Fixes PR25105 Patch by: Serge Guelton <serge.guelton@telecom-bretagne.eu> Differential Revision: https://reviews.llvm.org/D25443 llvm-svn: 283854
* Tune isHotFunction/isColdFunctionDehao Chen2016-10-111-6/+2
| | | | | | | | | | | | Summary: This patch sets function as hot if function's entry count is hot/cold. Reviewers: eraman, davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25048 llvm-svn: 283852
* Fix warning; NFCMatthias Braun2016-10-111-2/+2
| | | | llvm-svn: 283851
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