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* Fix warnings due to 132263; Thanks rdivacky.Nadav Rotem2011-05-291-2/+4
| | | | llvm-svn: 132285
* When generating against the Win64 EH scheme, set the handler to the GCC-specificCharles Davis2011-05-291-0/+7
| | | | | | | | | | | | | | | | handler. At this moment, only GCC-style exceptions are supported. Other kinds of exceptions, including "traditional" SEH and Microsoft Visual C++ exceptions, need more work--and an compiler exception model that isn't specific to GCC-style exceptions! In particular, I imagine that it would be possible to mix "traditional" SEH with GCC-style EH or Microsoft C++ EH. Currently LLVM has no way (beyond some target-specific defaults and whole-module compiler switches) of knowing which scheme to use when. llvm-svn: 132283
* Use %rbp on a 64 bit test.Rafael Espindola2011-05-291-1/+1
| | | | llvm-svn: 132279
* Fix to match the dwarf register numbers that gdb uses.Rafael Espindola2011-05-291-16/+16
| | | | llvm-svn: 132278
* Dwarf register 0 is r0, remove incorrect entries.Rafael Espindola2011-05-291-2/+2
| | | | llvm-svn: 132276
* Fix this to work correctly with phis; test case to follow if this successfullyJohn McCall2011-05-291-0/+1
| | | | | | fixes self-host. llvm-svn: 132275
* Remove the dwarf numbers from the D registers. They don't have dwarf numbersRafael Espindola2011-05-291-16/+16
| | | | | | | | and should probably be encoded as DW_OP_reg 32 DW_OP_piece 4 DW_OP_reg 33 llvm-svn: 132274
* Fix ARM fast isel to correctly flag memory operands to stores. This fixesCameron Zwarich2011-05-281-5/+7
| | | | | | -verify-machineinstrs failures on several tests. llvm-svn: 132268
* Refactor the type legalizer. Switch TargetLowering to a new enum - ↵Nadav Rotem2011-05-283-53/+62
| | | | | | | | | | | LegalizeTypeAction. This patch does not change the behavior of the type legalizer. The codegen produces the same code. This infrastructural change is needed in order to enable complex decisions for vector types (needed by the vector-select patch). llvm-svn: 132263
* Erase instructions _after_ checking their type.Benjamin Kramer2011-05-281-3/+4
| | | | llvm-svn: 132256
* Move ARM specific test into the ARM subdir.Benjamin Kramer2011-05-281-0/+0
| | | | llvm-svn: 132255
* ConstantFoldInstOperands doesn't like compares, hand it off to instsimplify ↵Benjamin Kramer2011-05-282-0/+20
| | | | | | | | instead. Fixes PR10040. llvm-svn: 132254
* Implement and document the llvm.eh.resume intrinsic, which isJohn McCall2011-05-284-139/+338
| | | | | | | | | | | | | | | | | transformed by the inliner into a branch to the enclosing landing pad (when inlined through an invoke). If not so optimized, it is lowered DWARF EH preparation into a call to _Unwind_Resume (or _Unwind_SjLj_Resume as appropriate). Its chief advantage is that it takes both the exception value and the selector value as arguments, meaning that there is zero effort in recovering these; however, the frontend is required to pass these down, which is not actually particularly difficult. Also document the behavior of landing pads a bit better, and make it clearer that it's okay that personality functions don't always land at landing pads. This is just a fact of life. Don't write optimizations that rely on pushing things over an unwind edge. llvm-svn: 132253
* Change how tblgen generates attributes for intrinsics to use a singleJohn McCall2011-05-284-59/+124
| | | | | | | | | switch. With this newfound organization, teach tblgen how not to give all intrinsics the 'nounwind' attribute. Introduce a new intrinsic, llvm.eh.resume, which does not have this attribute. Documentation and uses to follow. llvm-svn: 132252
* When generating code for Win64 EH, emit StartProc and EndProc directives.Charles Davis2011-05-283-0/+33
| | | | llvm-svn: 132250
* Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairsBruno Cardoso Lopes2011-05-286-5/+182
| | | | | | | | to load/store i64 values. Since there's no current support to explicitly declare such restrictions, implement it by using specific hardcoded register pairs during isel. llvm-svn: 132248
* This actually starts at offset 0, not 1.Eric Christopher2011-05-281-1/+1
| | | | llvm-svn: 132246
* Create two BlockInfo entries when a live range is discontinuous through a block.Jakob Stoklund Olesen2011-05-283-55/+71
| | | | | | | | | | | | | | | | | | | Delete the Kill and Def markers in BlockInfo. They are no longer necessary when BlockInfo describes a continuous live range. This only affects the relatively rare kind of basic block where a live range looks like this: |---x o---| Now live range splitting can pretend that it is looking at two blocks: |---x o---| This allows the code to be simplified a bit. llvm-svn: 132245
* Add SplitAnalysis::getNumLiveBlocks().Jakob Stoklund Olesen2011-05-283-5/+12
| | | | | | | | | | | It is important that this function returns the same number of live blocks as countLiveBlocks(CurLI) because live range splitting uses the number of live blocks to ensure it is making progress. This is in preparation of supporting duplicate UseBlock entries for basic blocks that have a virtual register live-in and live-out, but not live-though. llvm-svn: 132244
* Change the set of callee-saved registers for non-MIPS32 architectures specifiedAkira Hatanaka2011-05-281-9/+1
| | | | | | | | | in MipsRegisterInfo::getCalleeSavedRegs so that both registers paired for a double precision register get saved. llvm-svn: 132243
* Implement the 'M' output modifier for arm inline asm. This is fairlyEric Christopher2011-05-282-12/+54
| | | | | | | | | register allocation dependent and will occasionally break. WIP in the register allocator to model paired/etc registers. rdar://9119939 llvm-svn: 132242
* Add missing newlines.Chad Rosier2011-05-284-4/+4
| | | | llvm-svn: 132241
* Define a wrapper node for target constant nodes (tglobaladdr, etc.).Akira Hatanaka2011-05-285-16/+44
| | | | | | Need this to prevent emitting illegal conditional move instructions. llvm-svn: 132240
* Select DW_AT_const_value size based on global variable size.Devang Patel2011-05-281-5/+13
| | | | llvm-svn: 132239
* Add 132187 back now that the real problem is fixed.Rafael Espindola2011-05-281-45/+45
| | | | llvm-svn: 132238
* Fix test cases that were previously using grep to use FileCheckChad Rosier2011-05-2812-37/+56
| | | | llvm-svn: 132237
* Fix the root cause of the bootstrap failure:Rafael Espindola2011-05-282-8/+3
| | | | | | | | There was no way to check if a given register/mode pair was valid. We now return an error code (-2) instead of asserting. If anyone thinks that an assert at this point is really needed, we can autogen a hasValidDwarfRegNum instead. llvm-svn: 132236
* Fix the remaining atomic intrinsics to use the right register classes on Thumb2,Cameron Zwarich2011-05-272-10/+126
| | | | | | and add some basic tests for them. llvm-svn: 132235
* Stub out support for Win64-style exceptions. Note that this is merely usingCharles Davis2011-05-276-3/+102
| | | | | | | the Win64 EH mechanism to implement GCC-style exceptions. LLVM supports hardly anything else at this point! llvm-svn: 132234
* ARM asm parser wasn't able to parse a "mov" instruction while in ThumbBruno Cardoso Lopes2011-05-272-3/+8
| | | | | | | mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode, default to the Thumb 1 versions/encodings. llvm-svn: 132233
* It looks like 132187 might have broken the llvm-gcc bootstrap. Revert while ↵Rafael Espindola2011-05-271-45/+45
| | | | | | I check. llvm-svn: 132230
* Force a triple to make this test pass on Darwin.Eli Friedman2011-05-271-2/+2
| | | | llvm-svn: 132228
* Clean out the 2.9 Release Notes. Mostly limited to What's New in LLVMChad Rosier2011-05-271-265/+53
| | | | | | and enhancements in sub-project status updates. llvm-svn: 132227
* Add a GR32_NOREX_NOSP register class and fix a bug where ↵Cameron Zwarich2011-05-273-2/+58
| | | | | | | | | getMatchingSuperRegClass() was saying that the matching superregister class of GR32_NOREX in GR64_NOREX_NOSP is GR64_NOREX, which drops the NOSP constraint. This fixes PR10032. llvm-svn: 132225
* Fix a regression I recently introduced by removing DwarfRegNum ofRafael Espindola2011-05-272-1/+45
| | | | | | | | | | subregisters: When a value is in a subregister, at least report the location as being the superregister. We should extend the .td files to encode the bit range so that we can produce a DW_OP_bit_piece. llvm-svn: 132224
* Make size computation less brittle.Rafael Espindola2011-05-2710-82/+27
| | | | llvm-svn: 132222
* Add the suffix to the Win64 EH data sections' names if given. Add a test forCharles Davis2011-05-273-6/+61
| | | | | | this. XFAIL'd, because the COFF AsmParser can't handle .section yet. llvm-svn: 132220
* Refactor getActionType and getTypeToTransformTo ; place all of the 'decision'Nadav Rotem2011-05-275-92/+84
| | | | | | code in one place. Re-apply 131534 and fix the multi-step promotion of integers. llvm-svn: 132217
* Attempt to preserve debug line info in LICM; as the comment in the code ↵Eli Friedman2011-05-271-4/+14
| | | | | | | | says, it's hard to pick good line numbers for this transformation, but something is better than nothing. rdar://9143729 llvm-svn: 132215
* Typo is test caseChad Rosier2011-05-271-2/+2
| | | | llvm-svn: 132214
* Make room for register allocation to improve.Jakob Stoklund Olesen2011-05-271-1/+1
| | | | llvm-svn: 132213
* Add change of crc32 intrinsic to release notesChad Rosier2011-05-271-0/+6
| | | | llvm-svn: 132212
* Don't use movw / movt for iOS static codegen for now to workaround some ↵Evan Cheng2011-05-272-5/+6
| | | | | | tools issues. rdar://9514789 llvm-svn: 132211
* Delete a test that is no longer relevant.Jakob Stoklund Olesen2011-05-271-52/+0
| | | | | | | | | | | | | | | | | | | According to PR2536, the old spiller had trouble with the IMPLICIT_DEF in this code: %reg1028<def> = MOV16rm %reg0, 1, %reg0, <ga:g_5>, Mem:LD(2,2) [g_5 + 0] %reg1039<def> = IMPLICIT_DEF %reg1038<def> = INSERT_SUBREG %reg1039, %reg1028, 2 %reg1025<def> = AND32ri %reg1038, 65534, %%EFLAGS<imp-def> However, today we emit a zero-extending load instead: %vreg10<def> = MOVZX32rm16 %noreg, 1, %noreg, <ga:@g_5>, %noreg; %mem:LD2[@g_5] GR32:%vreg10 %vreg0<def> = AND32ri %vreg10, 65534, %%EFLAGS<imp-def,dead>; %GR32:%vreg0,%vreg10 This makes the test pointless since it no longer creates the spiller hazard. llvm-svn: 132210
* CRC32 intrinsics were renamed at revision 132163. This submissionChad Rosier2011-05-273-5/+21
| | | | | | | | fixes aliasing issues with the old and new names as well as adds test cases for the auto-upgrader. Fixes rdar 9472944. llvm-svn: 132207
* Keep this simple. Use DIType to get signness and size of a type. Based on ↵Devang Patel2011-05-271-18/+13
| | | | | | size, select appropraite form. llvm-svn: 132206
* Add a parameter to the Win64 EH section getters to get a section with aCharles Davis2011-05-276-22/+60
| | | | | | | | | | suffix (e.g. .xdata$myfunc). The suffix part isn't implemented yet, but I'll get to it in the next patch. Fix up all callers of the affected functions. Make them pass said suffix to the function. llvm-svn: 132205
* Add iOS testEvan Cheng2011-05-271-10/+29
| | | | llvm-svn: 132203
* Update this comment.Dan Gohman2011-05-271-1/+3
| | | | llvm-svn: 132202
* Don't sink or hoist debug info instrinsics; it isn't useful. This also ↵Eli Friedman2011-05-271-3/+6
| | | | | | | | prevents LICM sinking from erasing debug intrinsics which don't dominate any exit block of the loop. rdar://9143943 . llvm-svn: 132201
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