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* InstrProf: Make CounterMappingRegions less confusing to constructJustin Bogner2015-02-032-10/+32
| | | | | | | Creating empty and expansion regions is awkward with the current API. Expose static methods to make this simpler. llvm-svn: 228075
* [PBQP] Provide more information in the debug printsArnaud A. de Grandmaison2015-02-033-64/+88
| | | | | | Based on a patch by Jonas Paulsson llvm-svn: 228068
* Use ImmutableCallSite for statepoint verification.Philip Reames2015-02-031-17/+20
| | | | | | | | | | Patch by: Igor Laevsky "This change generalizes statepoint verification to use ImmutableCallSite instead of CallInst. This will allow to easily implement invoke statepoint verification (in a following change)." Differential Revision: http://reviews.llvm.org/D7308 llvm-svn: 228064
* [LV] Split off memcheck block really at the first checkAdam Nemet2015-02-031-1/+1
| | | | | | | | | | | I've noticed this while trying to move addRuntimeCheck to LoopAccessAnalysis. I think that the intention was to early exit from the overflow checking before the code for the memchecks. This is the entire reason why we compute FirstCheckInst but then we don't use that as the splitting instruction but the final check. Looks like an oversight. llvm-svn: 228056
* [x86] Fix signed vs. unsigned comparison.Chandler Carruth2015-02-031-1/+1
| | | | llvm-svn: 228055
* Fixed unused variable warning.Simon Pilgrim2015-02-031-2/+2
| | | | llvm-svn: 228054
* [Hexagon] Marking a bunch of non-encoded instructions with isCodeGenOnly = 1.Colin LeMahieu2015-02-034-45/+51
| | | | llvm-svn: 228050
* [CMake] add_llvm_library: don't use .imp suffix for import libraries on ↵Hans Wennborg2015-02-031-5/+0
| | | | | | | | | | | | | | | | | Windows (PR22334) This was added in r188351 to fix a naming conflict between the profile_rt-static and profile_rt-shared who both ended up in lib/profile_rt.lib. The change also affected other libraries (like libclang), and users are reporting that they find it surprising that there's no longer a libclang.lib. Since the profile_rt naming conflict doesn't seem to exist any more, I think we can remove this. Differential Revision: http://reviews.llvm.org/D7391 llvm-svn: 228049
* [PBQP] Constify Graph::getEdgeNode1Id and Graph::getEdgeNode2IdArnaud A. de Grandmaison2015-02-031-2/+2
| | | | llvm-svn: 228048
* [X86][SSE] psrl(w/d/q) and psll(w/d/q) bit shifts for SSE2Simon Pilgrim2015-02-039-15/+670
| | | | | | | | Patch to match cases where shuffle masks can be reduced to bit shifts. Similar to byte shift shuffle matching from D5699. Differential Revision: http://reviews.llvm.org/D6649 llvm-svn: 228047
* [PowerPC] Implement the vpopcnt instructions for POWER8Bill Schmidt2015-02-038-6/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by Kit Barton. Add the vector population count instructions for byte, halfword, word, and doubleword sizes. There are two major changes here: PPCISelLowering.cpp: Make CTPOP legal for vector types. PPCRegisterInfo.td: Added v2i64 to the VRRC register definition. This is needed for the doubleword variations of the integer ops that were added in P8. Test Plan Test the instruction vpcnt* encoding/decoding in ppc64-encoding-vmx.s Test the generation of the vpopcnt instructions for various vector data types. When adding the v2i64 type to the Vector Register set, I also needed to add the appropriate bit conversion patterns between v2i64 and the existing vector types. Testing for these conversions were also added in the test case by passing a different vector type as a parameter into the test functions. There is also a run step that will ensure the vpopcnt instructions are generated when the vsx feature is disabled. llvm-svn: 228046
* [fuzzer] Add proper dependensices to the fuzzer testsKostya Serebryany2015-02-033-1/+10
| | | | | | | | | | | | | | | | | | Summary: Make sure that FileCheck is built when running check-fuzzer Test Plan: run on bot: lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fuzzer Reviewers: samsonov Reviewed By: samsonov Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7387 llvm-svn: 228045
* [x86] Add two truly horrific test cases for the new vector shuffleChandler Carruth2015-02-031-0/+134
| | | | | | | lowering. I'm prepping patches to improve these, and this will let the delta of those patches show the improvement. =] llvm-svn: 228044
* [x86] Update the indent and layout of some tests in this file. NFCChandler Carruth2015-02-031-15/+15
| | | | | | | This is just to remove voise from using the update_llc_test_checks script. llvm-svn: 228043
* AsmParser: Recognize DW_TAG_* constantsDuncan P. N. Exon Smith2015-02-039-8/+57
| | | | | | | Recognize `DW_TAG_` constants in assembly, and output it by default for `GenericDebugNode`. llvm-svn: 228042
* IR: Assembly and bitcode for GenericDebugNodeDuncan P. N. Exon Smith2015-02-0311-13/+178
| | | | llvm-svn: 228041
* R600/SI: Remove the -CHECK suffix from all FileCheck prefixes in LIT testsMarek Olsak2015-02-0328-1414/+1414
| | | | llvm-svn: 228040
* R600/SI: Remove useless patterns in VALU which are already covered by SALUMarek Olsak2015-02-031-45/+16
| | | | | | | Also remove hasPostISelHook=1 from V_LSHL_B32. It's defined by InstSI already. Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 228039
* R600/SI: Rewrite VOP1InstSI to contain a pseudo and _si opcodeMarek Olsak2015-02-031-7/+23
| | | | | | | | | | | What this does is that if you accidentally select these instructions on VI, the code generation will fail, because the pseudo -> _vi mapping will be undefined. The idea is to be able to catch possible future bugs easily. Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 228038
* R600/SI: Fix B64 VALU shifts on VIMarek Olsak2015-02-037-40/+77
| | | | | | | SI only has standard versions. VI only has REV versions. Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 228037
* InstrProf: Remove CoverageMapping::HasCodeBefore, it isn't usedJustin Bogner2015-02-037-28/+14
| | | | | | | It's not entirely clear to me what this field was meant for, but it's always false. Remove it. llvm-svn: 228034
* [x86] Tweak my update script to use test case function names startingChandler Carruth2015-02-032-2/+5
| | | | | | | | | | | | with 'stress' to indicate that the specific output isn't interesting and relax them to only check the last instruction (a ret). I've updated the one test case that really uses this to name the one 'stress_test' which was actually producing output we can directly check. With this, the script doesn't introduce noise when run over the v16 test file. llvm-svn: 228033
* Support: Add string => unsigned mapping for DW_TAGDuncan P. N. Exon Smith2015-02-033-0/+28
| | | | | | Add `dwarf::getTag()` to translate from `StringRef` to `unsigned`. llvm-svn: 228031
* Support: Re-implement dwarf::TagString() using a .def file, NFCDuncan P. N. Exon Smith2015-02-033-161/+112
| | | | | | | | | Also re-implements the `dwarf::Tag` enumerator. I've moved the mock tags into the enumerator since there's no other way to do this. Really they shouldn't be used at all (they're just a hack to identify `MDNode`s, but we have a class hierarchy for that now). llvm-svn: 228030
* Support: Stop stringifying DW_TAG_{lo,hi}_userDuncan P. N. Exon Smith2015-02-033-2/+30
| | | | | | | | `dwarf::TagString()` shouldn't stringify `DW_TAG_lo_user` or `DW_TAG_hi_user`. These aren't actual tags; they're markers for the edge of vendor-specific tag regions. llvm-svn: 228029
* Fixed signed/unsigned comparison warning.Simon Pilgrim2015-02-031-1/+1
| | | | llvm-svn: 228027
* [Hexagon] Converting XTYPE/SHIFT intrinsics. Cleaning out old intrinsic ↵Colin LeMahieu2015-02-039-655/+213
| | | | | | patterns and updating tests. llvm-svn: 228026
* Fixed unused variable warning.Simon Pilgrim2015-02-031-2/+2
| | | | llvm-svn: 228025
* Allow PRE to insert no-cost phi nodesDaniel Berlin2015-02-032-44/+99
| | | | llvm-svn: 228024
* [X86][SSE] Added general integer shuffle matching for MOVQ instructionSimon Pilgrim2015-02-035-20/+68
| | | | | | This patch adds general shuffle pattern matching for the MOVQ zero-extend instruction (copy lower 64bits, zero upper) for all 128-bit integer vectors, it is added as a fallback test in lowerVectorShuffleAsZeroOrAnyExtend. llvm-svn: 228022
* [Hexagon] Updating XTYPE/PRED intrinsics.Colin LeMahieu2015-02-033-20/+192
| | | | llvm-svn: 228019
* [fuzzer] update the include line to use the new header nameKostya Serebryany2015-02-031-1/+1
| | | | llvm-svn: 228018
* Add straight-line strength reduction to LLVMJingyue Wu2015-02-038-0/+400
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Straight-line strength reduction (SLSR) is implemented in GCC but not yet in LLVM. It has proven to effectively simplify statements derived from an unrolled loop, and can potentially benefit many other cases too. For example, LLVM unrolls #pragma unroll foo (int i = 0; i < 3; ++i) { sum += foo((b + i) * s); } into sum += foo(b * s); sum += foo((b + 1) * s); sum += foo((b + 2) * s); However, no optimizations yet reduce the internal redundancy of the three expressions: b * s (b + 1) * s (b + 2) * s With SLSR, LLVM can optimize these three expressions into: t1 = b * s t2 = t1 + s t3 = t2 + s This commit is only an initial step towards implementing a series of such optimizations. I will implement more (see TODO in the file commentary) in the near future. This optimization is enabled for the NVPTX backend for now. However, I am more than happy to push it to the standard optimization pipeline after more thorough performance tests. Test Plan: test/StraightLineStrengthReduce/slsr.ll Reviewers: eliben, HaoLiu, meheff, hfinkel, jholewinski, atrick Reviewed By: jholewinski, atrick Subscribers: karthikthecool, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D7310 llvm-svn: 228016
* [Hexagon] Updating XTYPE/PERM intrinsics.Colin LeMahieu2015-02-032-88/+253
| | | | llvm-svn: 228015
* [X86][AVX2] Enabled shuffle matching for the AVX2 zero extension (128bit -> ↵Simon Pilgrim2015-02-034-11/+140
| | | | | | | | 256bit) vpmovzx* instructions. Differential Revision: http://reviews.llvm.org/D7251 llvm-svn: 228014
* Fix duplicated symbol error.Rafael Espindola2015-02-032-3/+3
| | | | llvm-svn: 228012
* Fix typo in test/CodeGen/X86/sibcall.ll (pr22331).Rafael Espindola2015-02-031-4/+4
| | | | llvm-svn: 228011
* [Hexagon] Adding missing vector multiply instruction encodings. Converting ↵Colin LeMahieu2015-02-036-185/+593
| | | | | | multiply intrinsics and updating tests. llvm-svn: 228010
* Merge consecutive 16-byte loads into one 32-byte load (PR22329)Sanjay Patel2015-02-033-87/+85
| | | | | | | | | | | | | | | | | | | | | This patch detects consecutive vector loads using the existing EltsFromConsecutiveLoads() logic. This fixes: http://llvm.org/bugs/show_bug.cgi?id=22329 This patch effectively reverts the tablegen additions of D6492 / http://reviews.llvm.org/rL224344 ...which in hindsight were a horrible hack. The test cases that were added with that patch are simply modified to load from varying offsets of a base pointer. These loads did not match the existing tablegen patterns. A happy side effect of doing this optimization earlier is that we can now fold the load into a math op where possible; this is shown in some of the updated checks in the test file. Differential Revision: http://reviews.llvm.org/D7303 llvm-svn: 228006
* remove variable names from comments; NFCSanjay Patel2015-02-031-63/+57
| | | | | | | I didn't bother to fix the self-referential definitions and grammar because my eyes started to bleed. llvm-svn: 228004
* [LTO API] split lto_codegen_compile to lto_codegen_optimize andManman Ren2015-02-035-30/+128
| | | | | | | | | | | | | | | | | | | lto_codegen_compile_optimized. Also add lto_api_version. Before this commit, we can only dump the optimized bitcode after running lto_codegen_compile, but it includes some impacts of running codegen passes, one example is StackProtector pass. We will get assertion failure when running llc on the optimized bitcode, because StackProtector is effectively run twice. After splitting lto_codegen_compile, the linker can choose to dump the bitcode before running lto_codegen_compile_optimized. lto_api_version is added so ld64 can check for runtime-availability of the new API. rdar://19565500 llvm-svn: 228000
* Fix ProgramFiles path for 64-bit Windows installerHans Wennborg2015-02-031-0/+3
| | | | | | | | | | | If we are building an 64bit installer on Windows we have to adjust the Program Files path otherwise it uses the wrong Program Files (x86) directory. Related CMake bug report http://public.kitware.com/Bug/view.php?id=14211 Patch by Ismail Dönmez! llvm-svn: 227999
* [Hexagon] Converting complex number intrinsics and adding tests.Colin LeMahieu2015-02-033-95/+439
| | | | llvm-svn: 227995
* [Hexagon] Adding vector intrinsics for alu32/alu and xtype/alu.Colin LeMahieu2015-02-034-175/+657
| | | | llvm-svn: 227993
* [LoopVectorize] Fix rebase glitch in r227751Adam Nemet2015-02-032-6/+6
| | | | | | | | | LoopVectorizationLegality::{getNumLoads,getNumStores} should forward to LoopAccessAnalysis now. Thanks to Takumi for noticing this! llvm-svn: 227992
* Remove usernames from TODOs, NFCJingyue Wu2015-02-031-3/+2
| | | | | | making the style consistent with the rest llvm-svn: 227991
* R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VIMarek Olsak2015-02-035-13/+94
| | | | | | | | | | | | | | | This can happen when a REV instruction is commuted. The trick is not to define the _vi versions of instructions, which has these consequences: - code generation will always fail if a pseudo cannot be lowered (very useful to catch bugs where an unsupported instruction somehow makes it to the printer) - ability to query if a pseudo can be lowered, which is done in commuteOpcode to prevent REV from commuting to non-REV on VI Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 227990
* R600/SI: Remove VOP2_REV definitions from target-specific instructionsMarek Olsak2015-02-032-32/+22
| | | | | | | | | | | The getCommute* functions are only used with pseudos, so this commit doesn't change anything. The issue with missing non-rev versions of shift instructions on VI will fixed separately. Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 227989
* R600/SI: Trivial instruction definition corrections for VI (v2)Marek Olsak2015-02-032-12/+24
| | | | | | | | | | | | - V_MAC_LEGACY_F32 exists on VI, but it's VOP3-only. - Define CVT_PK opcodes which are different between SI and VI. These are unused. The idea is to define all chip differences. v2: keep V_MUL_LO_U32 Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 227988
* R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2Marek Olsak2015-02-032-2/+12
| | | | | | | | | | | | | These are VOP2 on SI and VOP3 on VI, and their pseudos are neither, which can be a problem. In order to make isVOP2 and isVOP3 queries behave as expected, the encoding must be determined first. This doesn't fix any known issue, but better safe than sorry. v2: add and use getMCOpcodeFromPseudo Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 227987
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