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* AVX512: Implement instructions encoding, lowering and intrinsicsIgor Breger2015-09-2015-69/+1277
| | | | | | | | | vinserti64x4, vinserti64x2, vinserti32x8, vinserti32x4, vinsertf64x4, vinsertf64x2, vinsertf32x8, vinsertf32x4 Added tests for encoding, lowering and intrinsics. Differential Revision: http://reviews.llvm.org/D11893 llvm-svn: 248111
* ARM: cleanup formattingSaleem Abdulrasool2015-09-201-2/+2
| | | | | | clang-format a line which was poorly formatted. NFC. llvm-svn: 248110
* [IndVars] Fix a bug in r248045.Sanjoy Das2015-09-202-14/+51
| | | | | | | | | | | | | | Because -indvars widens induction variables through arithmetic, `NeverNegative` cannot be a property of the `WidenIV` (a `WidenIV` manages information for all transitive uses of an IV being widened, including uses of `-1 * IV`). Instead it must live on `NarrowIVDefUse` which manages information for a specific def-use edge in the transitive use list of an induction variable. This change also adds a test case that demonstrates the problem with r248045. llvm-svn: 248107
* Fixup r248096, commit the *correct* test.Davide Italiano2015-09-191-2/+2
| | | | llvm-svn: 248097
* [obj2yaml] Fix "time of check to time of use" bug. Add a test.Davide Italiano2015-09-192-3/+3
| | | | llvm-svn: 248096
* [X86][AVX2] Use general sext IR for vpmovsx stack folding testsSimon Pilgrim2015-09-191-6/+3
| | | | llvm-svn: 248093
* [X86][SSE] Vectorize CTTZ + CTTZ_ZERO_UNDEFSimon Pilgrim2015-09-194-3197/+1123
| | | | | | | | | | Now that we have fast vector CTPOP implementations we can use this to speed up vector CTTZ using the pattern (cttz(x) = ctpop((x & -x) - 1)) Additionally, for AVX512CD that provides lzcnt instructions we can use the pattern (cttz_undef(x) = (width - 1) - ctlz(x & -x)) Differential Revision: http://reviews.llvm.org/D12663 llvm-svn: 248091
* [InstCombine] Use SimplifyDemandedVectorEltsLow helper function. NFCI.Simon Pilgrim2015-09-191-17/+8
| | | | | | Use the SimplifyDemandedVectorEltsLow helper function introduced in D12680. llvm-svn: 248089
* [CMake] Update LLVM_TEST_DEPENDS not to use macho-dump. It has been unused ↵NAKAMURA Takumi2015-09-191-1/+0
| | | | | | since r247235. llvm-svn: 248088
* AMDGPU: Remove dead codeMatt Arsenault2015-09-195-18/+2
| | | | | | | getCFGStructurizerRegClass is not used for SI, so move it into R600 specific stuff. llvm-svn: 248087
* NFC: Fix indentation and add braces to clarify nested of else-statement.Bob Wilson2015-09-191-2/+3
| | | | llvm-svn: 248086
* [PrologEpilogInserter] Minor refactoring.Maksim Panchenko2015-09-191-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D12924 llvm-svn: 248084
* Test commit. Fix comment. NFC.Maksim Panchenko2015-09-191-1/+1
| | | | llvm-svn: 248082
* [InstCombine] FoldICmpCstShrCst failed for ashr when comparing against -1David Majnemer2015-09-192-1/+10
| | | | | | | | | (icmp eq (ashr C1, %V) -1) may have multiple answers if C1 is not a power of two and has the sign bit set. This fixes PR24873. llvm-svn: 248074
* [InstCombine] FoldICmpCstShrCst didn't handle icmps of -1 in the ashr case ↵David Majnemer2015-09-191-6/+10
| | | | | | correctly llvm-svn: 248073
* AMDGPU: Add failing testcase for live interval constructionMatt Arsenault2015-09-191-0/+29
| | | | llvm-svn: 248067
* [IndVars] Widen more comparisons for non-negative induction varsSanjoy Das2015-09-182-3/+154
| | | | | | | | | | | | | | | | | | | | Summary: If an induction variable is provably non-negative, its sign extension is equal to its zero extension. This means narrow uses like icmp slt iNarrow %indvar, %rhs can be widened into icmp slt iWide zext(%indvar), sext(%rhs) Reviewers: atrick, mcrosier, hfinkel Subscribers: hfinkel, reames, llvm-commits Differential Revision: http://reviews.llvm.org/D12745 llvm-svn: 248045
* Fix typo and test commitLuke Larson2015-09-181-1/+1
| | | | llvm-svn: 248042
* This code never uses r_addend, so it can just use Elf_Rel.Rafael Espindola2015-09-181-4/+2
| | | | llvm-svn: 248040
* [CMake] Adding ALWAYS_GENERATE option to symlink utility functions.Chris Bieneman2015-09-181-20/+33
| | | | | | This implements the behavior required for clang symlinks which should be always generated. llvm-svn: 248039
* [Object/ELF] Change comment to reflect reality.Davide Italiano2015-09-181-1/+1
| | | | llvm-svn: 248032
* Update edge weights properly when merging blocks in if-conversion.Cong Hou2015-09-183-6/+140
| | | | | | | | In if-conversion, there is a utility function MergeBlocks() that is used to merge blocks. However, when new edges are built in this function the edge weight is either not provided or not updated properly, leading to a modified CFG with incorrect edge weights. This patch corrects this issue. Differential Revision: http://reviews.llvm.org/D12513 llvm-svn: 248030
* Limit the range of processors supported by ARM fast isel to v6 orEric Christopher2015-09-183-36/+4
| | | | | | | | later as that's all that is tested right now. Fixes PR24858. llvm-svn: 248027
* Remove couple of new Bitcode enum vals that snuck in via r247927 (NFC)Teresa Johnson2015-09-181-3/+0
| | | | | | | These are meant to be part of the follow on patch I am sending for review shortly. llvm-svn: 248023
* Clean up: Refactoring the hardcoded value of 6 for ↵Larisse Voufo2015-09-185-11/+31
| | | | | | FindAvailableLoadedValue()'s parameter MaxInstsToScan. (Complete version of r247497. See D12886) llvm-svn: 248022
* Make MachineScheduler debug output less confusing.James Y Knight2015-09-183-6/+35
| | | | | | At least...a little bit. llvm-svn: 248020
* Scaling up values in ARMBaseInstrInfo::isProfitableToIfCvt() before they are ↵Cong Hou2015-09-186-23/+29
| | | | | | | | | | scaled by a probability to avoid precision issue. In ARMBaseInstrInfo::isProfitableToIfCvt(), there is a simple cost model in which the number of cycles is scaled by a probability to estimate the cost. However, when the number of cycles is small (which is usually the case), there is a precision issue after the computation. To avoid this issue, this patch scales those cycles by 1024 (chosen to make the multiplication a litter faster) before they are scaled by the probability. Other variables are also scaled up for the final comparison. Differential Revision: http://reviews.llvm.org/D12742 llvm-svn: 248018
* SelectionDAGDumper: Leave out the <multiple use> markersMatthias Braun2015-09-181-3/+0
| | | | | | | | | They mostly clutter the output while it is still possible to see which node has multiple users without them. Differential Revision: http://reviews.llvm.org/D12569 llvm-svn: 248013
* SelectionDAGDumper: Avoid unnecessary newlinesMatthias Braun2015-09-181-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before: t0 = EntryToken:ch t0: <multiple use> t0: <multiple use> t1 = CopyFromReg:v4f32,ch t0, Register:v4f32 %vreg0 t25 = IMPLICIT_DEF:v4f32 t26 = HADDPSrr:v4f32 t1, t25 t23 = CopyToReg:ch,glue t0, Register:v4f32 %XMM0, t26 t23: <multiple use> t23: <multiple use> t24 = RETQ:ch Register:v4f32 %XMM0, t23, t23:1 After: t0: <multiple use> t0: <multiple use> t1 = CopyFromReg:v4f32,ch t0, Register:v4f32 %vreg0 t26 = X86ISD::FHADD:v4f32 t1, undef:v4f32 t23 = CopyToReg:ch,glue t0, Register:v4f32 %XMM0, t26 t23: <multiple use> t21 = TargetConstant:i16<0> t23: <multiple use> t24 = X86ISD::RET_FLAG:ch t23, t21, Register:v4f32 %XMM0, t23:1 Differential Revision: http://reviews.llvm.org/D12568 llvm-svn: 248012
* SelectionDAGDumper: Hide [ID=X], [ORD=X] and source locations by default.Matthias Braun2015-09-183-18/+25
| | | | | | | | You can show them with the new -dag-dump-verbose switch. Differential Revision: http://reviews.llvm.org/D12566 llvm-svn: 248011
* SelectionDAG: Introduce PersistentID to SDNode for assert builds.Matthias Braun2015-09-187-10/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This gives us more human readable numbers to identify nodes in debug dumps. Before: 0x7fcbd9700160: ch = EntryToken 0x7fcbd985c7c8: i64 = Register %RAX ... 0x7fcbd9700160: <multiple use> 0x7fcbd985c578: i64,ch = MOV64rm 0x7fcbd985c6a0, 0x7fcbd985cc68, 0x7fcbd985c200, 0x7fcbd985cd90, 0x7fcbd985ceb8, 0x7fcbd9700160<Mem:LD8[@foo]> [ORD=2] 0x7fcbd985c8f0: ch,glue = CopyToReg 0x7fcbd9700160, 0x7fcbd985c7c8, 0x7fcbd985c578 [ORD=3] 0x7fcbd985c7c8: <multiple use> 0x7fcbd985c8f0: <multiple use> 0x7fcbd985c8f0: <multiple use> 0x7fcbd985ca18: ch = RETQ 0x7fcbd985c7c8, 0x7fcbd985c8f0, 0x7fcbd985c8f0:1 [ORD=3] Now: t0: ch = EntryToken t5: i64 = Register %RAX ... t0: <multiple use> t3: i64,ch = MOV64rm t10, t12, t11, t13, t14, t0<Mem:LD8[@foo]> [ORD=2] t6: ch,glue = CopyToReg t0, t5, t3 [ORD=3] t5: <multiple use> t6: <multiple use> t6: <multiple use> t7: ch = RETQ t5, t6, t6:1 [ORD=3] Differential Revision: http://reviews.llvm.org/D12564 llvm-svn: 248010
* [CMake] More cleanup of installing symlinks.Chris Bieneman2015-09-182-1/+7
| | | | | | | | In order to support building clang out-of-tree the install_symlink script needs to be installed, and it needs to be found by searching the CMAKE_MODULE_PATH. This change renames install_symlink -> LLVMInstallSymlink so it doesn't conflict with naming from other projects, and adds searching behavior in AddLLVM.cmake llvm-svn: 248009
* [AArch64] Improved bitfield instruction selection.Geoff Berry2015-09-183-11/+116
| | | | | | | | | | | | | | | | | | Summary: For bitfield insert OR matching, check both operands for larger pattern first before checking for smaller pattern. Add pattern for unsigned bitfield insert-in-zero done with SHL+AND. Resolves PR21631. Reviewers: jmolloy, t.p.northover Subscribers: aemerson, rengolin, llvm-commits, mcrosier Differential Revision: http://reviews.llvm.org/D12908 llvm-svn: 248006
* Remove temporary file on signal.Rafael Espindola2015-09-181-1/+6
| | | | | | Without this lld leaves temporary files behind when it crashes. llvm-svn: 247994
* Simplify SmallBitVector::applyMask by consolidating common code for 32- and ↵Yaron Keren2015-09-182-14/+13
| | | | | | | | | | | | | 64-bit builds and assert when mask is too large to apply in the small case, previously the extra words were silently ignored. clang-format the entire function to match current code standards. This is a rewrite of r247972 which was reverted in r247983 due to warning and possible UB on 32-bits hosts. llvm-svn: 247993
* [mips][microMIPS] Fix an invalid read for lwm32 and reserved reglist values.Daniel Sanders2015-09-182-0/+10
| | | | | | | | | | | | | | | Summary: Some values of 'reglist' are reserved and cause the disassembler to read past the end of the Regs array. Treat lwm32's containing reserved values as invalid instructions. Reviewers: zoran.jovanovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12959 llvm-svn: 247990
* [AArch64] Reorder cases to improve readability. NFC.Chad Rosier2015-09-181-9/+9
| | | | llvm-svn: 247989
* [AArch64] Remove some redundant cases. NFC.Chad Rosier2015-09-181-16/+8
| | | | llvm-svn: 247988
* Silencing a -Wsign-compare warning; NFC.Aaron Ballman2015-09-181-1/+1
| | | | llvm-svn: 247986
* [LazyValueInfo] Report nonnull range for nonnull pointersIgor Laevsky2015-09-182-2/+25
| | | | | | | | | | | | Currently LazyValueInfo will report only alloca's as having nonnull range. For loads with !nonnull metadata it will bailout with no additional information. Same is true for calls returning nonnull pointers. This change extends LazyValueInfo to handle additional nonnull instructions. Differential Revision: http://reviews.llvm.org/D12932 llvm-svn: 247985
* Support align attribute for return valuesArtur Pilipenko2015-09-183-1/+20
| | | | | | | | Reviewed By: reames Differential Revision: http://reviews.llvm.org/D12844 llvm-svn: 247984
* Reverting r247972 (and subordinate commit r247972) as the 32-bit left-shift ↵Aaron Ballman2015-09-182-10/+12
| | | | | | is undefined behavior on implementations where uinptr_t is 32-bits. One such platform is Windows, MSVC, x86. llvm-svn: 247983
* Nit cleanup in LangRef about dereferenceable metadataArtur Pilipenko2015-09-181-5/+6
| | | | | | | | Reviewed By: vsk Differential Revision: http://reviews.llvm.org/D12847 llvm-svn: 247982
* [Support] Reapply r245289 "Always wait for GraphViz before opening the viewer"Michael Kruse2015-09-181-1/+1
| | | | | | | | | | | | | The change was accidentally undone by r245290. Original log message: When calling DisplayGraph and a PS viewer is chosen, two programs are executed: The GraphViz generator and the PostScript viewer. Always wait for the generator to finish to ensure that the .ps file is written before opening the viewer for that file. DisplayGraph's wait parameter refers to whether to wait until the user closes the viewer. This happened on Windows and if none of the options to open the .dot file directly applies, also on Linux. Differential Revision: http://reviews.llvm.org/D11876 llvm-svn: 247980
* [llvm-mc-fuzzer] Document llvm-mc-fuzzer in LibFuzzer.rst.Daniel Sanders2015-09-181-0/+17
| | | | llvm-svn: 247979
* [WinEH] Moved funclet pads should be in relative orderDavid Majnemer2015-09-183-9/+57
| | | | | | | | | | | We shifted the MachineBasicBlocks to the end of the MachineFunction in DFS order. This will not ensure that MachineBasicBlocks which fell through to one another will remain contiguous. Instead, implement a stable sort algorithm for iplist. This partially reverts commit r214150. llvm-svn: 247978
* Fix BitVectorTest on 32-bit hosts after r247972.Yaron Keren2015-09-181-2/+2
| | | | | | | We can't apply two words of 32-bit mask in the small case where the internal storage is just one 32-bit word. llvm-svn: 247974
* Simplify SmallBitVector::applyMask by consolidating common code for 32-bit ↵Yaron Keren2015-09-182-12/+10
| | | | | | | | | | | | | and 64-bit builds. Extend mask value to 64 bits before taking its complement and assert when mask is too large to apply in the small case (previously the extra words were silently ignored). http://reviews.llvm.org/D11890 Patch by James Touton! llvm-svn: 247972
* Remove trailing whitespace from the old Orc Kaleidoscope examples.Lang Hames2015-09-184-448/+444
| | | | llvm-svn: 247971
* Whitespace. Indent with spaces instead of a tab.Bob Wilson2015-09-181-1/+1
| | | | llvm-svn: 247969
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