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* Revert two bad commits.JF Bastien2015-08-249-101/+28
| | | | | | | | | | Summary: I forgot to squash git commits before doing an svn dcommit of D12219. Reverting, and re-submitting. Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D12298 llvm-svn: 245886
* Missing print.JF Bastien2015-08-243-17/+19
| | | | llvm-svn: 245883
* callJF Bastien2015-08-248-8/+166
| | | | llvm-svn: 245882
* [X86][SSE] Added tests for zero-extension vector shuffles that don't extend ↵Simon Pilgrim2015-08-241-0/+280
| | | | | | starting from the 0'th lane. llvm-svn: 245878
* [WebAssembly] Make the assembly printer indent instructions.Dan Gohman2015-08-241-0/+2
| | | | llvm-svn: 245875
* LTO: Rename mergedModule variables to MergedModule to prepare for ownership ↵Peter Collingbourne2015-08-241-20/+17
| | | | | | | | change. Also convert a few loops to range-for loops and correct a comment. llvm-svn: 245874
* Report an error if a SHT_SYMTAB_SHNDX section has the wrong size.Rafael Espindola2015-08-243-8/+22
| | | | llvm-svn: 245873
* [WebAssembly] CodeGen support for __builtin_wasm_page_size()Dan Gohman2015-08-244-1/+40
| | | | llvm-svn: 245872
* fix typo; NFCSanjay Patel2015-08-241-1/+1
| | | | llvm-svn: 245869
* [PPC64LE] Fix PR24546 - Swap optimization and debug valuesBill Schmidt2015-08-242-0/+119
| | | | | | | | | | This patch fixes PR24546, which demonstrates a segfault during the VSX swap removal pass. The problem is that debug value instructions were not excluded from the list of instructions to be analyzed for webs of related computation. I've added the test case from the PR as a crash test in test/CodeGen/PowerPC. llvm-svn: 245862
* [WebAssembly] Skeleton FastISel supportDan Gohman2015-08-248-1/+143
| | | | llvm-svn: 245860
* [WebAssembly] Implement floating point rounding operators.Dan Gohman2015-08-244-12/+96
| | | | llvm-svn: 245859
* [docs][PerformanceTips] Framing the generic IR tipsPhilip Reames2015-08-241-14/+32
| | | | llvm-svn: 245858
* [docs][PerformanceTips] Point people towards llvm-devPhilip Reames2015-08-241-0/+7
| | | | llvm-svn: 245856
* [docs] Further organization of the Performance Tips documentPhilip Reames2015-08-241-15/+54
| | | | | | | | Arranging the language specific property section into readable groupings and adding a couple of notes about pass order, extensions, and the like. For the record, suggestion for word smithing are welcomed. I'm happy to revise; I'm just trying to get *something* in place. llvm-svn: 245855
* [docs] Organize the 'Performance Tips' pagePhilip Reames2015-08-241-46/+54
| | | | | | This change just groups the suggestions by broad topic. I'm planning a couple of follow on changes to improve the readability of this document. llvm-svn: 245854
* [WebAssembly] Tell TargetTransformInfo about popcnt and sqrt.Dan Gohman2015-08-242-4/+10
| | | | llvm-svn: 245853
* [WebAssembly] Use the checked form of MachineFunction::getSubtarget. NFC.Dan Gohman2015-08-242-4/+3
| | | | llvm-svn: 245852
* [WebAssembly] Implement the is_zero_undef forms of cttz and ctlzDan Gohman2015-08-243-0/+42
| | | | llvm-svn: 245851
* [sanitizers] Add DFSan support for AArch64 42-bit VMAAdhemerval Zanella2015-08-241-0/+14
| | | | | | | | | This patch adds support for dfsan on aarch64-linux with 42-bit VMA (current default config for 64K pagesize kernels). The support is enabled by defining the SANITIZER_AARCH64_VMA to 42 at build time for both clang/llvm and compiler-rt. The default VMA is 39 bits. llvm-svn: 245840
* [X86] Add support for mmword memory operand size for Intel-syntax x86 assemblyMichael Zuckerman2015-08-242-1/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D12151 llvm-svn: 245835
* Add DAG optimisation for FP16_TO_FPOliver Stannard2015-08-242-0/+57
| | | | | | | | | | | | | | The FP16_TO_FP node only uses the bottom 16 bits of its input, so the following pattern can be optimised by removing the AND: (FP16_TO_FP (AND op, 0xffff)) -> (FP16_TO_FP op) This is a common pattern for ARM targets when functions have __fp16 arguments, as they are passed as floats (so that they get passed in the correct registers), but then bitcast and truncated to ignore the top 16 bits. llvm-svn: 245832
* [ARM] Use AEABI helpers for i64 div and remScott Douglass2015-08-243-18/+117
| | | | | | Differential Revision: http://reviews.llvm.org/D12232 llvm-svn: 245830
* [ARM] Refactor LowerDivRem before adding LowerREM (nfc)Scott Douglass2015-08-241-17/+36
| | | | | | Differential Revision: http://reviews.llvm.org/D12230 llvm-svn: 245829
* first commit to llvmMichael Zuckerman2015-08-241-0/+1
| | | | llvm-svn: 245825
* Require Dominator Tree For SROA, improve compile-timeMehdi Amini2015-08-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TL-DR: SROA is followed by EarlyCSE which requires the DominatorTree. There is no reason not to require it up-front for SROA. Some history is necessary to understand why we ended-up here. r123437 switched the second (Legacy)SROA in the optimizer pipeline to use SSAUpdater in order to avoid recomputing the costly DominanceFrontier. The purpose was to speed-up the compile-time. Later r123609 removed the need for the DominanceFrontier in (Legacy)SROA. Right after, some cleanup was made in r123724 to remove any reference to the DominanceFrontier. SROA existed in two flavors: SROA_SSAUp and SROA_DT (the latter replacing SROA_DF). The second argument of `createScalarReplAggregatesPass` was renamed from `UseDomFrontier` to `UseDomTree`. I believe this is were a mistake was made. The pipeline was not updated and the call site was still: PM->add(createScalarReplAggregatesPass(-1, false)); At that time, SROA was immediately followed in the pipeline by EarlyCSE which required alread the DominatorTree. Not requiring the DominatorTree in SROA didn't save anything, but unfortunately it was lost at this point. When the new SROA Pass was introduced in r163965, I believe the goal was to have an exact replacement of the existing SROA, this bug slipped through. You can see currently: $ echo "" | clang -x c++ -O3 -c - -mllvm -debug-pass=Structure ... ... FunctionPass Manager SROA Dominator Tree Construction Early CSE After this patch: $ echo "" | clang -x c++ -O3 -c - -mllvm -debug-pass=Structure ... ... FunctionPass Manager Dominator Tree Construction SROA Early CSE This improves the compile time from 88s to 23s for PR17855. https://llvm.org/bugs/show_bug.cgi?id=17855 And from 113s to 12s for PR16756 https://llvm.org/bugs/show_bug.cgi?id=16756 Reviewers: chandlerc Differential Revision: http://reviews.llvm.org/D12267 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 245820
* remove FIXME; fixed by r245733Sanjay Patel2015-08-231-1/+0
| | | | llvm-svn: 245819
* [IR] Cleanup EH instructions a little bitDavid Majnemer2015-08-233-20/+6
| | | | | | Just a cosmetic change, no functionality change is intended. llvm-svn: 245818
* [DAGCombiner] Fold CONCAT_VECTORS of bitcasted EXTRACT_SUBVECTORSimon Pilgrim2015-08-232-2/+27
| | | | | | Minor generalization of D12125 - peek through any bitcast to the original vector that we're extracting from. llvm-svn: 245814
* [llvm-readobj/ELF] Factor out common code.Davide Italiano2015-08-231-12/+11
| | | | llvm-svn: 245813
* [dwarfdump] Do not apply relocations in mach-o files if there is no ↵Frederic Riss2015-08-233-0/+35
| | | | | | | | | | | | | | LoadedObjectInfo. Not only do we not need to do anything to read correct values from the object files, but the current logic actually wrongly applies twice the section base address when there is no LoadedObjectInfo passed to the DWARFContext creation (as the added test shows). Simply do not apply any relocations on the mach-o debug info if there is no load offset to apply. llvm-svn: 245807
* [dsymutil] Remove old ODR uniquing testsFrederic Riss2015-08-2316-1190/+0
| | | | | | | These tests have been obsoleted by the refactored versions introduced in the previous commit. llvm-svn: 245804
* [dsymutil] Refactor ODR uniquing tests to be more readable.Frederic Riss2015-08-2311-0/+385
| | | | | | | | | This patch adds all the refactored tests in new files, the old tests will be removed by a followup commit. Thanks to D. Blaikie for all the feedback. llvm-svn: 245803
* [LangRef] Fix sphinx warningJoseph Tremoulet2015-08-231-1/+1
| | | | | | Fix invalid inline literal introduced in r245797 llvm-svn: 245801
* Add missing break in AArch64DAGToDAGISel::Select() switch caseMehdi Amini2015-08-231-0/+1
| | | | | | | Reported by coverity. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 245800
* Do not use dyn_cast<> after isa<>Mehdi Amini2015-08-231-1/+1
| | | | | | | Reported by coverity. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 245799
* [WinEH] Require token linkage in EH pad/ret signaturesJoseph Tremoulet2015-08-2321-532/+738
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: WinEHPrepare is going to require that cleanuppad and catchpad produce values of token type which are consumed by any cleanupret or catchret exiting the pad. This change updates the signatures of those operators to require/enforce that the type produced by the pads is token type and that the rets have an appropriate argument. The catchpad argument of a `CatchReturnInst` must be a `CatchPadInst` (and similarly for `CleanupReturnInst`/`CleanupPadInst`). To accommodate that restriction, this change adds a notion of an operator constraint to both LLParser and BitcodeReader, allowing appropriate sentinels to be constructed for forward references and appropriate error messages to be emitted for illegal inputs. Also add a verifier rule (noted in LangRef) that a catchpad with a catchpad predecessor must have no other predecessors; this ensures that WinEHPrepare will see the expected linear relationship between sibling catches on the same try. Lastly, remove some superfluous/vestigial casts from instruction operand setters operating on BasicBlocks. Reviewers: rnk, majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12108 llvm-svn: 245797
* Update test case so it passes the verifierDavid Blaikie2015-08-221-1/+1
| | | | | | | | | Some debug info was drastically out of date, from the days where we used to emit a list of length one (with a single null entry) rather than an empty list (or, more recently, no list at all) for list fields that have no elements. llvm-svn: 245796
* Verifier: Don't crash on null entries in debug info retained types listDavid Blaikie2015-08-222-1/+11
| | | | | | | | There was already a good error path for this. Added a test for it & made a minor code change to ensure the error path was actually reached, rather than crashing before we got that far. llvm-svn: 245795
* [llvm-readobj] Test --macho-data-in-code option.Davide Italiano2015-08-221-18/+35
| | | | | | | As added bonus this converts an existing test from macho-dump to llvm-readobj. Only 66 to go. llvm-svn: 245791
* [NVPTX] Allow undef value as global initializerJingyue Wu2015-08-222-3/+17
| | | | | | | | | | | | | | | | | | Summary: __shared__ variable may now emit undef value as initializer, do not throw error on that. Test Plan: test/CodeGen/NVPTX/global-addrspace.ll Patch by Xuetian Weng Reviewers: jholewinski, tra, jingyue Subscribers: llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D12242 llvm-svn: 245785
* [CMake] add_llvm_external_project: Just warn about nonexistent directories.NAKAMURA Takumi2015-08-221-1/+5
| | | | | | These entries were generated accidentally. llvm-svn: 245783
* [CMake] Make LLVM_EXTERNAL_*_SOURCE_DIR consistent against older buildsites.NAKAMURA Takumi2015-08-221-20/+24
| | | | | | | | | | | | | | | | | | If corresponding in-tree subdirectory exists, just ignore LLVM_EXTERNAL* stuff. Otherwise, set LLVM_TOOL_*_BUILD ON/OFF properly according to LLVM_EXTERNAL_*. This makes easier to walk among old revisions *without* deleteing CMakeCache.txt. Before r242059, LLVM_EXTERNAL_* was working like; if(EXISTS ${*_SOURCE_DIR}/CMakeLists.txt) set(*_BUILD ON CACHE) if(*_BUILD is ON) add_subdirectory(*_SOURCE_DIR) endif() endif() llvm-svn: 245782
* LTO: Maintain target triple, FeatureStr and CGOptLevel in the module or ↵Peter Collingbourne2015-08-222-19/+25
| | | | | | | | LTOCodeGenerator. This makes it easier to create new TargetMachines on demand. llvm-svn: 245781
* AMDGPU: Allow specifying different opcode on VI for SMRD/SMEMMatt Arsenault2015-08-222-15/+21
| | | | | | | | Although the basic s_load_* instructions happen to use the same opcode, some of the special case SMRD instructions have different opcodes. llvm-svn: 245775
* AMDGPU: Improve accuracy of instruction rates for some FP instructionsMatt Arsenault2015-08-224-13/+33
| | | | llvm-svn: 245774
* AMDGPU: Use DFS to avoid second loop over functionMatt Arsenault2015-08-221-15/+13
| | | | llvm-svn: 245772
* AMDGPU: Make sure to run verifier after SIFixSGPRLiveRangesMatt Arsenault2015-08-221-1/+1
| | | | llvm-svn: 245769
* AMDGPU: Improve debug printing in SIFixSGPRLiveRangesMatt Arsenault2015-08-221-6/+15
| | | | llvm-svn: 245768
* AMDGPU: Move CI instructions into CIInstructions.tdMatt Arsenault2015-08-222-70/+69
| | | | | | There are still a couple of CI patterns left in SIInstructions. llvm-svn: 245767
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