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* [objc-arc-opts] Add comment to BBState making it clear that ↵Michael Gottesman2013-05-131-0/+6
| | | | | | get{TopDown,BottomUp}PtrState will create a new PtrState object if it does not find a PtrState for Arg. llvm-svn: 181726
* Fix goofy commentary in PPCTargetObjectFile.cpp.Bill Schmidt2013-05-131-2/+2
| | | | llvm-svn: 181725
* PPC64: Constant initializers with dynamic relocations go in .data.rel.ro.Bill Schmidt2013-05-135-0/+121
| | | | | | | | | | | | | | | | | | | | | This fixes warning messages observed in the oggenc application test in projects/test-suite. Special handling is needed for the 64-bit PowerPC SVR4 ABI when a constant is initialized with a pointer to a function in a shared library. Because a function address is implemented as the address of a function descriptor, the use of copy relocations can lead to problems with initialization. GNU ld therefore replaces copy relocations with dynamic relocations to be resolved by the dynamic linker. This means the constant cannot reside in the read-only data section, but instead belongs in .data.rel.ro, which is designed for constants containing dynamic relocations. The implementation creates a class PPC64LinuxTargetObjectFile inheriting from TargetLoweringObjectFileELF, which behaves like its parent except to place constants of this sort into .data.rel.ro. The test case is reduced from the oggenc application. llvm-svn: 181723
* Remove redundant variable introduced by r181682.Bob Wilson2013-05-131-1/+0
| | | | llvm-svn: 181721
* [objc-arc] Move the before optimization statistics gathering phase out of ↵Michael Gottesman2013-05-131-8/+7
| | | | | | | | | | | OptimizeIndividualCalls. This makes the statistics gathering completely independent of the actual optimization occuring, preventing any sort of bleeding over from occuring. Additionally, it simplifies a switch statement in the non-statistic gathering case. llvm-svn: 181719
* [mips] Add option -mno-ldc1-sdc1.Akira Hatanaka2013-05-134-4/+120
| | | | | | | | This option is used when the user wants to avoid emitting double precision FP loads and stores. Double precision FP loads and stores are expanded to single precision instructions after register allocation. llvm-svn: 181718
* Fix a bug that APFloat::fusedMultiplyAdd() mistakenly evaluate "14.5f * ↵Shuxin Yang2013-05-132-2/+50
| | | | | | -14.5f + 225.0f" to 225.0f. llvm-svn: 181715
* [mips] Define a helper function which creates an instruction with the sameAkira Hatanaka2013-05-132-0/+19
| | | | | | operands as the prototype instruction but with a different opcode. llvm-svn: 181714
* [mips] Rename functions. No functionality changes.Akira Hatanaka2013-05-137-29/+29
| | | | llvm-svn: 181713
* Remove unused fields and arguments.Rafael Espindola2013-05-133-13/+6
| | | | llvm-svn: 181706
* The purpose of the patch is to fix the syntax of ARM mrc and mrc2 ↵Mihai Popa2013-05-136-14/+58
| | | | | | instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. llvm-svn: 181705
* Correctly preserve the input chain for potential tailcall nodes whoseLang Hames2013-05-132-1/+18
| | | | | | | | | | | | return values are bitcasts. The chain had previously been being clobbered with the entry node to the dag, which sometimes caused other code in the function to be erroneously deleted when tailcall optimization kicked in. <rdar://problem/13827621> llvm-svn: 181696
* Suppress GCC compiler warnings in release builds about variables that are onlyDuncan Sands2013-05-133-0/+3
| | | | | | read in asserts. llvm-svn: 181689
* SLPVectorizer: Swap LHS and RHS. No functionality change.Nadav Rotem2013-05-131-4/+4
| | | | llvm-svn: 181684
* Fix PR15950 A bug in DAG Combiner about undef maskHao Liu2013-05-132-10/+35
| | | | llvm-svn: 181682
* Remove the MachineMove class.Rafael Espindola2013-05-1338-177/+169
| | | | | | | | | | | | It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. llvm-svn: 181680
* XFAIL this test for mingw too.Rafael Espindola2013-05-131-1/+1
| | | | llvm-svn: 181678
* SLPVectorizer: Fix a bug in the code that generates extracts for values with ↵Nadav Rotem2013-05-122-9/+57
| | | | | | | | multiple users. The external user does not have to be in lane #0. We have to save the lane for each scalar so that we know which vector lane to extract. llvm-svn: 181674
* SLPVectorizer: Clear the map that maps between scalars to vectors after each ↵Nadav Rotem2013-05-121-0/+1
| | | | | | | | round of vectorization. Testcase in the next commit. llvm-svn: 181673
* InstCombine: Flip the order of two urem transformsDavid Majnemer2013-05-122-6/+20
| | | | | | | | | | | | | | There are two transforms in visitUrem that conflict with each other. *) One, if a divisor is a power of two, subtracts one from the divisor and turns it into a bitwise-and. *) The other unwraps both operands if they are surrounded by zext instructions. Flipping the order allows the subtraction to go beneath the sign extension. llvm-svn: 181668
* LoopVectorize: Use the widest induction variable typeArnold Schwaighofer2013-05-112-21/+138
| | | | | | | | | | | | | | | | | | | | | | Use the widest induction type encountered for the cannonical induction variable. We used to turn the following loop into an empty loop because we used i8 as induction variable type and truncated 1024 to 0 as trip count. int a[1024]; void fail() { int reverse_induction = 1023; unsigned char forward_induction = 0; while ((reverse_induction) >= 0) { forward_induction++; a[reverse_induction] = forward_induction; --reverse_induction; } } radar://13862901 llvm-svn: 181667
* LoopVectorize: Use variable instead of repeated function callArnold Schwaighofer2013-05-111-3/+4
| | | | | | No functionality change intended. llvm-svn: 181666
* LoopVectorize: Use IRBuilder interface in more placesArnold Schwaighofer2013-05-111-25/+13
| | | | | | No functionality change intended. llvm-svn: 181665
* Correct parameter name in doc comment to match declaration.David Blaikie2013-05-111-1/+1
| | | | | | (review feedback on r181632 from Dmitri) llvm-svn: 181664
* StringRefize some debug accel table bits.Benjamin Kramer2013-05-113-7/+7
| | | | llvm-svn: 181663
* InstCombine: Turn urem to bitwise-and more oftenDavid Majnemer2013-05-112-22/+53
| | | | | | | Use isKnownToBeAPowerOfTwo in visitUrem so that we may more aggressively fold away urem instructions. llvm-svn: 181661
* Change getFrameMoves to return a const reference.Rafael Espindola2013-05-1110-58/+52
| | | | | | | To add a frame now there is a dedicated addFrameMove which also takes care of constructing the move itself. llvm-svn: 181657
* Remove more dead code.Rafael Espindola2013-05-112-13/+0
| | | | llvm-svn: 181656
* Add -mtriple=mipsel-linux-gnu to the test so that the compiler doesReed Kotler2013-05-111-4/+4
| | | | | | not think it can support small data sections. llvm-svn: 181654
* Remove dead code.Rafael Espindola2013-05-102-82/+0
| | | | llvm-svn: 181649
* SLPVectorizer: Add support for trees with external users.Nadav Rotem2013-05-103-13/+60
| | | | | | | | | | | | | For example: bar() { int a = A[i]; int b = A[i+1]; B[i] = a; B[i+1] = b; foo(a); <--- a is used outside the vectorized expression. } llvm-svn: 181648
* Add a debug printNadav Rotem2013-05-101-0/+2
| | | | llvm-svn: 181647
* Add an additional testcase for PR15882.Nadav Rotem2013-05-101-0/+45
| | | | llvm-svn: 181646
* Checkin in of first of several patches to finish implementation ofReed Kotler2013-05-1013-16/+359
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). llvm-svn: 181641
* Micro-optimization: don't shift an entire bitcode record over to get the code.Jordan Rose2013-05-101-3/+10
| | | | | | | | | | | Previously, BitstreamCursor read an abbreviated record by splatting the whole thing into a data vector, then extracting and removing the /first/ element. Now, it reads the first element--the record code--separately from the actual field values. No (intended) functionality change. llvm-svn: 181639
* Give the test from r181632 a target triple.David Blaikie2013-05-101-1/+1
| | | | llvm-svn: 181637
* PR14492: Debug Info: Support for values of non-integer non-type template ↵David Blaikie2013-05-106-9/+112
| | | | | | | | | | parameters. This is only tested for global variables at the moment (& includes tests for the unnamed parameter case, since apparently this entire function was completely untested previously) llvm-svn: 181632
* Fix unused variable error.Jyotsna Verma2013-05-101-2/+1
| | | | | | | Earlier, this variable was used in an assert and was causing failure on darwin. llvm-svn: 181630
* Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore.Jyotsna Verma2013-05-104-707/+81
| | | | | | No functionality change. llvm-svn: 181628
* Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.Jyotsna Verma2013-05-109-703/+198
| | | | llvm-svn: 181624
* Fix the R600 build.Rafael Espindola2013-05-102-3/+2
| | | | llvm-svn: 181621
* [ms-inline asm] Fix a crasher when we fail on a direct match.Chad Rosier2013-05-103-6/+12
| | | | | | | | | | | | | | | | | | The issue was that the MatchingInlineAsm and VariantID args to the MatchInstructionImpl function weren't being set properly. Specifically, when parsing intel syntax, the parser thought it was parsing inline assembly in the at&t dialect; that will never be the case. The crash was caused when the emitter tried to emit the instruction, but the operands weren't set. When parsing inline assembly we only set the opcode, not the operands, which is used to lookup the instruction descriptor. rdar://13854391 and PR15945 Also, this commit reverts r176036. Now that we're correctly parsing the intel syntax the pushad/popad don't match properly. I've reimplemented that fix using a MnemonicAlias. llvm-svn: 181620
* Remove unused argument.Rafael Espindola2013-05-1024-38/+31
| | | | llvm-svn: 181618
* Fix MCJITCAPITest.cpp unit test on Windows.Andrew Kaylor2013-05-101-0/+2
| | | | | | MCJIT on Windows requires an explicit target triple with "-elf" appended to generate objects in ELF format. The common test framework was setting up this triple, but it wasn't passed to the C API in the test. llvm-svn: 181614
* Better output for long help strings for command-line options.Alexander Kornienko2013-05-102-9/+18
| | | | | | | | | | | | | | | | | | | | | Summary: This patch allows using \n inside long help strings for command-line options, so that all lines are equally indented. This is not a perfect solution, as we don't (and probably don't want to) know about terminal width, but it allows to format long help strings somehow readable without manually padding them with spaces. A motivating example is -help output from clang-format (source code in tools/clang-format/ClangFormat.cpp, see cl options offset, length, style, and dump-config). Reviewers: atrick, alexfh Reviewed By: alexfh CC: llvm-commits, rafael Differential Revision: http://llvm-reviews.chandlerc.com/D779 llvm-svn: 181608
* Remove unused function.Rafael Espindola2013-05-102-11/+0
| | | | llvm-svn: 181606
* InstCombine: Don't claim to be able to evaluate any shl in a zexted type.Benjamin Kramer2013-05-102-1/+39
| | | | | | | | | | The shift amount may be larger than the type leading to undefined behavior. Limit the transform to constant shift amounts. While there update the bits to clear in the result which may enable additional optimizations. PR15959. llvm-svn: 181604
* Implement AsmParser for ARM unwind directives.Logan Chien2013-05-1024-27/+2587
| | | | | | | | | | | | | | | | | | | This commit implements the AsmParser for fnstart, fnend, cantunwind, personality, handlerdata, pad, setfp, save, and vsave directives. This commit fixes some minor issue in the ARMELFStreamer: * The switch back to corresponding section after the .fnend directive. * Emit the unwind opcode while processing .fnend directive if there is no .handlerdata directive. * Emit the unwind opcode to .ARM.extab while processing .handlerdata even if .personality directive does not exist. llvm-svn: 181603
* XFAILing this test on Win32 to unbreak the build bots.Aaron Ballman2013-05-101-1/+1
| | | | llvm-svn: 181600
* DAGCombiner: Generate a correct constant for vector types when folding (xor ↵Benjamin Kramer2013-05-102-2/+12
| | | | | | | | (and)) into (and (not)). PR15948. llvm-svn: 181597
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