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* Don't try to split weird critical edges that really aren't:Jakob Stoklund Olesen2010-11-021-2/+12
| | | | | | | | | | | | | | | BB#1: derived from LLVM BB %bb.nph28 Live Ins: %AL Predecessors according to CFG: BB#0 TEST8rr %reg16384<kill>, %reg16384, %EFLAGS<imp-def>; GR8:%reg16384 JNE_4 <BB#2>, %EFLAGS<imp-use,kill> JMP_4 <BB#2> Successors according to CFG: BB#2 BB#2 These double CFG edges only ever occur in bugpoint-generated code, so there is no need to attempt something clever. llvm-svn: 117992
* Attempt to provide correct encodings for a number of other vld1 variants, ↵Owen Anderson2010-11-021-45/+59
| | | | | | | | which we can't test since we can neither generate nor parse them at the moment. llvm-svn: 117988
* Tidy up.Jim Grosbach2010-11-021-3/+0
| | | | llvm-svn: 117987
* Add aesthetic break.Owen Anderson2010-11-021-1/+1
| | | | llvm-svn: 117986
* Tweak to fix spelling and grammar in comment.Jim Grosbach2010-11-021-3/+3
| | | | llvm-svn: 117985
* Add correct NEON encodings for the "multiple single elements" form of vld.Owen Anderson2010-11-026-18/+72
| | | | llvm-svn: 117984
* MachineLICM should not claim to be preserving the CFG when it can split criticalJakob Stoklund Olesen2010-11-011-1/+0
| | | | | | edges on demand. llvm-svn: 117982
* Be more precise about verifying missing kill flags.Jakob Stoklund Olesen2010-11-011-2/+4
| | | | | | | It is legal for an instruction to have two operands using the same register, only one a kill. This is interpreted as a kill. llvm-svn: 117981
* When inserting copies during splitting, always use the parent register as theJakob Stoklund Olesen2010-11-012-19/+16
| | | | | | | | | | | | source, and let rewrite() clean it up. This way, kill flags on the inserted copies are fixed as well during rewrite(). We can't just assume that all the copies we insert are going to be kills since critical edges into loop headers sometimes require both source and dest to be live out of a block. llvm-svn: 117980
* fix computation of ambiguous instructions to not ignore the mnemonic.Chris Lattner2010-11-011-3/+7
| | | | | | FWIW, X86 has 254 ambiguous instructions. llvm-svn: 117979
* Explicitly check for non-consant reference in an LDRi12 instruction. Add FIXMEJim Grosbach2010-11-011-1/+10
| | | | | | for handling the fixup necessary. llvm-svn: 117978
* Remove unused function.Jim Grosbach2010-11-011-13/+0
| | | | llvm-svn: 117977
* Add support for alignment operands on VLD1-lane instructions.Bob Wilson2010-11-013-35/+59
| | | | | | This is another part of the fix for Radar 8599955. llvm-svn: 117976
* Add VLD1-lane testcases for quad-register types.Bob Wilson2010-11-011-0/+27
| | | | llvm-svn: 117975
* Missed reverting this bit.Bill Wendling2010-11-011-1/+1
| | | | llvm-svn: 117971
* Minor cleanup.Bill Wendling2010-11-011-11/+7
| | | | llvm-svn: 117969
* give MatchableInfo::Operand a constructorChris Lattner2010-11-011-11/+7
| | | | llvm-svn: 117968
* rearrange a bit.Chris Lattner2010-11-011-50/+55
| | | | llvm-svn: 117967
* Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.Bob Wilson2010-11-016-4/+120
| | | | llvm-svn: 117964
* Add kill flag verification.Jakob Stoklund Olesen2010-11-011-2/+13
| | | | | | | | At least X86FloatingPoint requires correct kill flags after register allocation, and targets using register scavenging benefit. Conservative kill flags are not enough. llvm-svn: 117960
* Update kill flags while rewriting instructions after splitting.Jakob Stoklund Olesen2010-11-011-0/+3
| | | | llvm-svn: 117959
* Move the machine operand MC encoding patterns to the parent classes.Bill Wendling2010-11-012-41/+36
| | | | llvm-svn: 117956
* Use ARM-style comments.Bill Wendling2010-11-011-62/+61
| | | | llvm-svn: 117955
* When folding away a (shl (shr)) pair, we need to check that the bits that ↵Owen Anderson2010-11-012-1/+21
| | | | | | | | will BECOME the low bits are zero, not that the current low bits are zero. Fixes <rdar://problem/8606771>. llvm-svn: 117953
* use our fancy new MnemonicAlias mechanism to remove a bunch of hacksChris Lattner2010-11-012-51/+16
| | | | | | from X86AsmParser.cpp llvm-svn: 117952
* When we look at instructions to convert to setting the 's' flag, we need to lookBill Wendling2010-11-014-18/+23
| | | | | | | | | | | | | | | | | | | | | | | | at more than those which define CPSR. You can have this situation: (1) subs ... (2) sub r6, r5, r4 (3) movge ... (4) cmp r6, 0 (5) movge ... We cannot convert (2) to "subs" because (3) is using the CPSR set by (1). There's an analogous situation here: (1) sub r1, r2, r3 (2) sub r4, r5, r6 (3) cmp r4, ... (5) movge ... (6) cmp r1, ... (7) movge ... We cannot convert (1) to "subs" because of the intervening use of CPSR. llvm-svn: 117950
* Don't assign new registers created during a split to the same stack slot, butJakob Stoklund Olesen2010-11-013-16/+3
| | | | | | give them individual stack slots once the are actually spilled. llvm-svn: 117945
* Add basic LiveStacks verification.Jakob Stoklund Olesen2010-11-011-0/+20
| | | | | | | When an instruction refers to a spill slot with a LiveStacks entry, check that the spill slot is live at the instruction. llvm-svn: 117944
* Use ARM-style comment syntax.Owen Anderson2010-11-0118-626/+626
| | | | llvm-svn: 117941
* NEON does not support truncating vector stores. Radar 8598391.Bob Wilson2010-11-012-0/+14
| | | | llvm-svn: 117940
* Covert this test to .s form.Owen Anderson2010-11-012-103/+19
| | | | llvm-svn: 117939
* Convert this test to .s form.Owen Anderson2010-11-012-538/+108
| | | | llvm-svn: 117938
* Covert this test to .s form.Owen Anderson2010-11-012-215/+46
| | | | llvm-svn: 117937
* Add FIXME.Jim Grosbach2010-11-011-0/+1
| | | | llvm-svn: 117936
* Covert this test to .s form.Owen Anderson2010-11-012-449/+98
| | | | llvm-svn: 117935
* Fix test.Rafael Espindola2010-11-011-1/+1
| | | | llvm-svn: 117932
* Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gatesJim Grosbach2010-11-012-20/+22
| | | | | | | codegen using the patterns; the latter gates the assembler recognizing the instruction. llvm-svn: 117931
* Write the line info to .debug_line.Rafael Espindola2010-11-012-0/+31
| | | | llvm-svn: 117930
* Mark ARM subtarget features that are available for the assembler.Jim Grosbach2010-11-0123-36/+42
| | | | llvm-svn: 117929
* trailing whitespaceJim Grosbach2010-11-011-5/+5
| | | | llvm-svn: 117927
* Move EmitInstruction to MCObjectStreamer so that ELF and MachO can share it.Rafael Espindola2010-11-015-69/+50
| | | | llvm-svn: 117925
* The T2 extract/pack instructions are only valid in Thumb2 mode. Mark theJim Grosbach2010-11-011-12/+14
| | | | | | patterns as such llvm-svn: 117923
* Add support for .value.Rafael Espindola2010-11-012-0/+6
| | | | llvm-svn: 117922
* Implement .weakref.Rafael Espindola2010-11-0112-6/+372
| | | | llvm-svn: 117911
* Move instruction encoding bits into the parent class and remove the temporaryBill Wendling2010-11-012-273/+224
| | | | | | | *_Encode classes. These instructions are the only ones which use those classes, so a subclass isn't necessary. llvm-svn: 117906
* More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when theBill Wendling2010-11-012-4/+5
| | | | | | peephole optimizer is disabled. That's not good at all. llvm-svn: 117905
* The testcase is now XFAILed. Sorry about the breakage.Bill Wendling2010-11-011-0/+2
| | | | llvm-svn: 117904
* Disable because peephole is disabled.Bill Wendling2010-11-011-0/+1
| | | | llvm-svn: 117903
* "mov[zs]x (mem), GR16" are not ambiguous: the memChris Lattner2010-11-012-0/+12
| | | | | | must be 8 bits. Support this memory form. llvm-svn: 117902
* Implement enough of the missing instalias support to getChris Lattner2010-11-016-16/+96
| | | | | | | | | | | | | | | | | | aliases installed and working. They now work when the matched pattern and the result instruction have exactly the same operand list. This is now enough for us to define proper aliases for movzx and movsx, implementing rdar://8017633 and PR7459. Note that we do not accept instructions like: movzx 0(%rsp), %rsi GAS accepts this instruction, but it doesn't make any sense because we don't know the size of the memory operand. It could be 8/16/32 bits. llvm-svn: 117901
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