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* [PM] Port StripDeadPrototypes to the new pass managerJustin Bogner2015-10-308-24/+82
| | | | | | | This is a really straightforward port. Also adds a test for the pass, since it only seemed to be tested tangentially before. llvm-svn: 251726
* [PM] Port ADCE to the new pass managerJustin Bogner2015-10-307-28/+76
| | | | llvm-svn: 251725
* Whitespace. NFCJustin Bogner2015-10-304-8/+6
| | | | llvm-svn: 251724
* PM: Print the IR unit's name in debug output. NFCJustin Bogner2015-10-301-1/+2
| | | | llvm-svn: 251723
* Implemented the code to make llvm-nm’s -g option work.Kevin Enderby2015-10-304-0/+9
| | | | | | | | | | | | | While llvm-nm parses the -g option and has help that describes it as: -extern-only - Show only external symbols There is no code in the program to use the boolean valve it sets from the command line. rdar://23261095 llvm-svn: 251718
* [FunctionAttrs] Separate another chunk of the logic for functionattrsChandler Carruth2015-10-301-10/+16
| | | | | | | | | | | from its pass harness by providing a lambda to query for AA results. This allows the legacy pass to easily provide a lambda that uses the special helpers to construct function AA results from a legacy CGSCC pass. With the new pass manager (the next patch) the lambda just directly wraps the intuitive query API. llvm-svn: 251715
* [WebAssembly] Fix import statementJF Bastien2015-10-302-10/+13
| | | | | | | | | | Summary: Imports should be generated like (param i32 f32...) not (param i32) (param f32) ... Author: binji Reviewers: jfb Subscribers: jfb, dschuff llvm-svn: 251714
* ARM: add extra test for watchOS ABITim Northover2015-10-301-0/+153
| | | | llvm-svn: 251705
* [SCEV] Generalize the SCEV algorithm for creating expressions for PHI nodesSilviu Baranga2015-10-302-14/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When forming expressions for phi nodes having an incoming value from outside the loop A and a value coming from the previous iteration B we were forming an AddRec if: - B was an AddRec - the value A was equal to the value for B at iteration -1 (or equal to the value of B shifted by one iteration, at iteration 0) In this case, we were computing the expression to be the expression of B, shifted by one iteration. This changes generalizes the logic above by removing the restriction that B needs to be an AddRec. For this we introduce two expression rewriters that allow us to - shift an expression by one iteration - get the value of an expression at iteration 0 This allows us to get SCEV expressions for PHI nodes when these expressions are not AddRecExprs. Reviewers: sanjoy Subscribers: llvm-commits, sanjoy Differential Revision: http://reviews.llvm.org/D14175 llvm-svn: 251700
* Recommit r251680 (also need to update clang test)Dehao Chen2015-10-302-11/+110
| | | | | | | | | | | | | | | | | | | Update the discriminator assignment algorithm * If a scope has already been assigned a discriminator, do not reassign a nested discriminator for it. * If the file and line both match, even if the column does not match, we should assign a new discriminator for the stmt. original code: ; #1 int foo(int i) { ; #2 if (i == 3 || i == 5) return 100; else return 99; ; #3 } ; i == 3: discriminator 0 ; i == 5: discriminator 2 ; return 100: discriminator 1 ; return 99: discriminator 3 llvm-svn: 251689
* Remove oneline.ll test.Dehao Chen2015-10-301-0/+0
| | | | llvm-svn: 251688
* [X86] Use is128BitVector/is256BitVector/is512BitVector in place of ↵Craig Topper2015-10-301-17/+16
| | | | | | getSizeInBits == in some places. NFC llvm-svn: 251687
* [X86] Minor formatting fixes. NFC.Craig Topper2015-10-301-9/+8
| | | | llvm-svn: 251686
* Revert r251680:Dehao Chen2015-10-302-110/+11
| | | | | | | | | | | | | | | | | | | Update the discriminator assignment algorithm * If a scope has already been assigned a discriminator, do not reassign a nested discriminator for it. * If the file and line both match, even if the column does not match, we should assign a new discriminator for the stmt. original code: ; #1 int foo(int i) { ; #2 if (i == 3 || i == 5) return 100; else return 99; ; #3 } ; i == 3: discriminator 0 ; i == 5: discriminator 2 ; return 100: discriminator 1 ; return 99: discriminator 3 llvm-svn: 251685
* [Orc] Expose the compile callback API through the C bindings.Lang Hames2015-10-305-35/+153
| | | | llvm-svn: 251683
* [X86] Use MVT instead of EVT in some places. NFCCraig Topper2015-10-301-37/+41
| | | | | | Prior to this the compiled code probably had extra checks for extended types that won't ever execute. llvm-svn: 251682
* Update the discriminator assignment algorithmDehao Chen2015-10-302-11/+110
| | | | | | | | | | | | | | | | | * If a scope has already been assigned a discriminator, do not reassign a nested discriminator for it. * If the file and line both match, even if the column does not match, we should assign a new discriminator for the stmt. original code: ; #1 int foo(int i) { ; #2 if (i == 3 || i == 5) return 100; else return 99; ; #3 } ; i == 3: discriminator 0 ; i == 5: discriminator 2 ; return 100: discriminator 1 ; return 99: discriminator 3 llvm-svn: 251680
* [MC] Make another header NDEBUG-free.Davide Italiano2015-10-301-4/+0
| | | | llvm-svn: 251679
* Let the users of LLVMSymbolizer decide whether they want to symbolize ↵Alexey Samsonov2015-10-303-21/+42
| | | | | | | | | | | inlined frames. Introduce LLVMSymbolizer::symbolizeInlinedCode() instead of switching on PrintInlining option passed to the constructor. This will be needed once we retrun structured data (instead of std::string) from LLVMSymbolizer and move printing logic out. llvm-svn: 251675
* llvm/ExecutionEngine/Orc/LogicalDylib.h: Satisfy Modules.NAKAMURA Takumi2015-10-301-0/+4
| | | | llvm-svn: 251674
* [LLVMSymbolize] Simplify SymbolizableObjectFile::symbolizeInlinedCode(). NFC.Alexey Samsonov2015-10-302-17/+13
| | | | llvm-svn: 251672
* Revert "Don't assert if materializing before seeing any function bodies"Filipe Cabecinhas2015-10-303-8/+1
| | | | | | This reverts r251667 since it broke the bots. llvm-svn: 251671
* [LLVMSymbolize] Move printing the description of a global into a separate ↵Alexey Samsonov2015-10-296-21/+40
| | | | | | function. NFC. llvm-svn: 251669
* Don't assert if materializing before seeing any function bodiesFilipe Cabecinhas2015-10-293-1/+8
| | | | | | | | | This assert was reachable from user input. A minimized test case (no FUNCTION_BLOCK_ID record) is attached. Bug found with afl-fuzz llvm-svn: 251667
* Revert "[ARM] Remove XFAIL on test/CodeGen/Generic/MachineBranchProb.ll"Weiming Zhao2015-10-291-1/+2
| | | | | | | | | | | | | | | | | | Summary: This reverts commit 79c37e1a4ff1e634da8f95322f080601b4c815fc. This test passes locally but fails on the community buildbot. So we will let it XFAIL for now. Patched by Mandeep Singh Grang (mgrang@codeaurora.org) Reviewers: kparzysz, weimingz Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14189 llvm-svn: 251664
* [LLVMSymbolize] Move ModuleInfo into a separate class (SymbolizableModule).Alexey Samsonov2015-10-296-270/+416
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is mostly NFC. It is a first step in cleaning up LLVMSymbolize library. It removes "ModuleInfo" class which bundles together ObjectFile and its debug info context in favor of: * abstract SymbolizableModule in public headers; * SymbolizableObjectFile subclass in implementation. Additionally, SymbolizableObjectFile is now created via factory, so we can properly detect object parsing error at this stage instead of keeping the broken half-parsed object. As a next step, we would be able to propagate the error all the way back to the library user. Further improvements might include: * factoring out the logic of finding appropriate file with debug info for a given object file, and caching all parsed object files into a separate class [A]. * factoring out DILineInfo rendering [B]. This would make what is now a heavyweight "LLVMSymbolizer" a relatively straightforward class, that calls into [A] to turn filepath into a SymbolizableModule, delegates actual symbolization to concrete SymbolizableModule implementation, and lets [C] render the result. Reviewers: dblaikie, echristo, rafael Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14099 llvm-svn: 251662
* [X86][SSE] Added load+sext tests for 16i1->16i8 and 32i1->32i8Simon Pilgrim2015-10-291-1/+1245
| | | | llvm-svn: 251661
* [X86][SSE] Shuffle blends with zeroSimon Pilgrim2015-10-293-25/+105
| | | | | | | | This patch generalizes the zeroing of vector elements with the BLEND instructions. Currently a zero vector will only blend if the shuffled elements are correctly inline, this patch recognises when a vector input is zero (or zeroable) and modifies a local copy of the shuffle mask to support a blend. As a zeroable vector input may not be all zeroes, the zeroable vector is regenerated if necessary. Differential Revision: http://reviews.llvm.org/D14050 llvm-svn: 251659
* [Orc] Teach IndirectStubsManager to manage an expandable pool of stubs, ratherLang Hames2015-10-294-20/+83
| | | | | | | than a pre-allocated slab of stubs. Also add a convenience method for creating a single stub, rather than a whole block a time. llvm-svn: 251658
* clang-format lib/Transforms/Utils/AddDiscriminators.cppDehao Chen2015-10-291-12/+11
| | | | llvm-svn: 251656
* Fix test check label.Teresa Johnson2015-10-291-2/+2
| | | | | | | | | | | | | | | | | | | | | Summary: I noticed when manually modifying this test that it was passing when I expected it to fail. Looks like the combination of LABEL and NOT on the check does not work. This can also be seen when running FileCheck with only that one -check-prefix (removing the additional -check-prefix=B): /usr/local/google/home/tejohnson/llvm/llvm_11_build/./bin/llvm-link -S -internalize -only-needed /usr/local/google/home/tejohnson/llvm/llvm_11_build/test/Linker/Output/link-flags.ll.tmp.b.bc /usr/local/google/home/tejohnson/llvm/llvm_11_build/test/Linker/Output/link-flags.ll.tmp.c.bc | /usr/local/google/home/tejohnson/llvm/llvm_11_build/./bin/FileCheck /usr/local/google/home/tejohnson/llvm/llvm_11/test/Linker/link-flags.ll -check-prefix=CN error: no check strings found with prefix 'CN:' The CN prefix checks don't in fact need "LABEL" so remove that. Reviewers: tra Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14173 llvm-svn: 251655
* [ARM] Remove XFAIL on test/CodeGen/Generic/MachineBranchProb.llWeiming Zhao2015-10-291-2/+1
| | | | | | | | | | | | Summary: Refer PR23377. This test was XFAIL'ed for Hexagon as well as ARM. But it has now started passing for ARM. Reviewers: hans, rengolin, aemerson, kparzysz Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D14155 llvm-svn: 251652
* [Orc] Rename IndirectStubsManagerBase method 'init' to 'createStubs'.Lang Hames2015-10-293-4/+4
| | | | llvm-svn: 251641
* [FunctionAttrs] Provide a single SCC node set to all of theChandler Carruth2015-10-291-91/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | transformations in FunctionAttrs rather than building a new one each time. This isn't trivial because there are different heuristics from different passes for exactly what set they want. The primary difference is whether an *overridable* function completely disables the synthesis of attributes. I've modeled this by directly testing for overridable, and using the common set that excludes external and opt-none functions. This does cause some changes by disabling more optimizations in the face of opt-none. Specifically, we were still optimizing *calls* to opt-none functions based on their attributes, just not the bodies. It seems better to be conservative on both fronts given the intended semanticas here (best effort to not assume or disturb anything). I've not tried to test this change as it seems complex, brittle, and not important to the implicit contract of opt-none. Instead, it seems more like a choice that should be dictated by the simplified implementation and the change to be acceptable differences within the space of opt-none. A big benefit here is that these transformations no longer rely on the legacy pass manager's SCC types, they just work on generic sets of function pointers. This will make it easy to re-use their logic in the new pass manager. I've also made the transforms static functions instead of members where trivial while I was touching the signatures. llvm-svn: 251640
* Revert r251593.Diego Novillo2015-10-291-1/+1
| | | | | | | The patch in r251593 was only papering over the problem. The actual fix was committed in r251623. llvm-svn: 251635
* [SystemZ] Make the CCRegs regclass non-allocatable.Jonas Paulsson2015-10-295-5/+41
| | | | | | | | | | | | | | | | | | | | | This was discovered to be necessary while running memchr-01.ll with -verify-machinstrs, because it is not allowed to have a phys reg live accross block boundaries while on SSA form, if the register is allocatable (expect in entry block and landing pads). In this test case, stringRRE pseudos are expanded after isel by adding a loop block which produces a live out CC register. To make the test pass, it was also necessary to not say that StringRRELoop pseudo uses R0L, this is only true for the StringRRE opcode. -verify-machineinstrs added to memchr-01.ll test. New test case int-cmp-51.ll to test that MachineCSE can eliminate an identical compare (which it couldn't do before). Reviewed by Ulrich Weigand llvm-svn: 251634
* AMDGPU/SI: handle undef for llvm.SI.packf16Marek Olsak2015-10-292-0/+33
| | | | llvm-svn: 251632
* AMDGPU/SI: use S_OR for fneg (fabs f32)Marek Olsak2015-10-292-20/+10
| | | | llvm-svn: 251631
* AMDGPU/SI: use S_AND for i1 truncMarek Olsak2015-10-292-6/+6
| | | | llvm-svn: 251630
* [mips] wrong opcode for ll/sc instructions on mipsr6 when -integrated-as is usedZoran Jovanovic2015-10-292-5/+42
| | | | | | | | | | | | | | | Summary: This commit resolves wrong opcodes for ll and sc instructions for r6 architecutres, which were generated in method MipsTargetLowering::emitAtomicBinary. Author: Jelena.Losic Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D13593 llvm-svn: 251629
* Recognize that ARM1176JZ[F]-S support TrustZoneArtyom Skrobov2015-10-294-2/+7
| | | | | | | | | | | | | | Summary: ARMv6KZ cores were set up incorrectly in ARM.td; also, the SMI mnemonic (the old name for SMC, as defined in ARMv6KZ) wasn't supported. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14154 llvm-svn: 251627
* [sanitizer] [msan] Unify aarch64 mappingAdhemerval Zanella2015-10-291-21/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch unify the 39-bit and 42-bit mapping for aarch64 to use only one instrumentation algorithm. This removes compiler flag SANITIZER_AARCH64_VMA requirement for MSAN on aarch64. The mapping to use now is for 39 and 42-bits: 0x00000000000ULL-0x01000000000ULL MappingDesc::INVALID 0x01000000000ULL-0x02000000000ULL MappingDesc::SHADOW 0x02000000000ULL-0x03000000000ULL MappingDesc::ORIGIN 0x03000000000ULL-0x04000000000ULL MappingDesc::SHADOW 0x04000000000ULL-0x05000000000ULL MappingDesc::ORIGIN 0x05000000000ULL-0x06000000000ULL MappingDesc::APP 0x06000000000ULL-0x07000000000ULL MappingDesc::INVALID 0x07000000000ULL-0x08000000000ULL MappingDesc::APP And only for 42-bits: 0x08000000000ULL-0x09000000000ULL MappingDesc::INVALID 0x09000000000ULL-0x0A000000000ULL MappingDesc::SHADOW 0x0A000000000ULL-0x0B000000000ULL MappingDesc::ORIGIN 0x0B000000000ULL-0x0F000000000ULL MappingDesc::INVALID 0x0F000000000ULL-0x10000000000ULL MappingDesc::APP 0x10000000000ULL-0x11000000000ULL MappingDesc::INVALID 0x11000000000ULL-0x12000000000ULL MappingDesc::APP 0x12000000000ULL-0x17000000000ULL MappingDesc::INVALID 0x17000000000ULL-0x18000000000ULL MappingDesc::SHADOW 0x18000000000ULL-0x19000000000ULL MappingDesc::ORIGIN 0x19000000000ULL-0x20000000000ULL MappingDesc::INVALID 0x20000000000ULL-0x21000000000ULL MappingDesc::APP 0x21000000000ULL-0x26000000000ULL MappingDesc::INVALID 0x26000000000ULL-0x27000000000ULL MappingDesc::SHADOW 0x27000000000ULL-0x28000000000ULL MappingDesc::ORIGIN 0x28000000000ULL-0x29000000000ULL MappingDesc::SHADOW 0x29000000000ULL-0x2A000000000ULL MappingDesc::ORIGIN 0x2A000000000ULL-0x2B000000000ULL MappingDesc::APP 0x2B000000000ULL-0x2C000000000ULL MappingDesc::INVALID 0x2C000000000ULL-0x2D000000000ULL MappingDesc::SHADOW 0x2D000000000ULL-0x2E000000000ULL MappingDesc::ORIGIN 0x2E000000000ULL-0x2F000000000ULL MappingDesc::APP 0x2F000000000ULL-0x39000000000ULL MappingDesc::INVALID 0x39000000000ULL-0x3A000000000ULL MappingDesc::SHADOW 0x3A000000000ULL-0x3B000000000ULL MappingDesc::ORIGIN 0x3B000000000ULL-0x3C000000000ULL MappingDesc::APP 0x3C000000000ULL-0x3D000000000ULL MappingDesc::INVALID 0x3D000000000ULL-0x3E000000000ULL MappingDesc::SHADOW 0x3E000000000ULL-0x3F000000000ULL MappingDesc::ORIGIN 0x3F000000000ULL-0x40000000000ULL MappingDesc::APP And although complex it provides a better memory utilization that previous one. llvm-svn: 251624
* Fix use-after-free. Thanks ASAN for giving me a detailed report :-).Daniel Jasper2015-10-291-2/+2
| | | | llvm-svn: 251623
* [mips] Check the register class before replacing materializations of zero ↵Vasileios Kalintiris2015-10-292-0/+13
| | | | | | | | | | | | | | | | | | | | | | with $zero in microMIPS. Summary: The microMIPS register class GPRMM16 does not contain the $zero register. However, MipsSEDAGToDAGISel::replaceUsesWithZeroReg() would replace uses of the $dst register: [d]addiu, $dst, $zero, 0 with the $zero register, without checking for membership in the register class of the target machine operand. Reviewers: dsanders Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13984 llvm-svn: 251622
* [MachineVerifier] Analyze MachineMemOperands for mem-to-mem moves.Jonas Paulsson2015-10-292-7/+26
| | | | | | | | | | | | | Since the verifier will give false reports if it incorrectly thinks MI is loading or storing using an FI, it is necessary to scan memoperands and find out how the FI is used in the instruction. This should be relatively rare. Needed to make CodeGen/SystemZ/spill-01.ll pass, which now runs with this flag. Reviewed by Quentin Colombet. llvm-svn: 251620
* OrcJITTests: Update libdeps corresponding to r251604.NAKAMURA Takumi2015-10-291-0/+2
| | | | llvm-svn: 251619
* Revert the revision 251592 as it fails a test on some platforms.Cong Hou2015-10-293-143/+32
| | | | llvm-svn: 251617
* Revert "ScheduleDAGInstrs: Remove IsPostRA flag"Matthias Braun2015-10-294-22/+38
| | | | | | | | It broke 3 arm testcases. This reverts commit r251608. llvm-svn: 251615
* Fix an unused variable warning which broke the clang-cmake-mips builderPhilip Reames2015-10-291-1/+1
| | | | llvm-svn: 251614
* [WebAssembly] Update opcode name format for conversionsJF Bastien2015-10-293-48/+56
| | | | | | | | | | | | Summary: Conversion opcode name format should be f64.convert_u/i64 not f64_convert_u Author: s3ththompson Reviewers: jfb Subscribers: sunfish, jfb, llvm-commits, dschuff Differential Revision: http://reviews.llvm.org/D14160 llvm-svn: 251613
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