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* [SDAG] Fix Stale SDNode usage in visitANDNirav Dave2017-03-282-4/+35
| | | | | | | | | | | | | | | Reorder CombineTo Calls to prevent potential use of deleted node. Fixes PR32372. Reviewers: jnspaulsson, RKSimon, uweigand, jonpa Reviewed By: jonpa Subscribers: jonpa, llvm-commits Differential Revision: https://reviews.llvm.org/D31346 llvm-svn: 298920
* [x86] add AVX2 run to show 256-bit opportunity; NFCSanjay Patel2017-03-281-17/+17
| | | | llvm-svn: 298918
* Fix signed/unsigned comparison warningSimon Pilgrim2017-03-281-2/+2
| | | | llvm-svn: 298917
* [SDAG] Minor cleanup of variable usage. NFC.Nirav Dave2017-03-281-2/+2
| | | | llvm-svn: 298916
* [X86][SSE] Begin merging vector shuffle to BLEND for lowering and combining.Simon Pilgrim2017-03-281-70/+82
| | | | | | Split off matchVectorShuffleAsBlend from lowerVectorShuffleAsBlend for reuse in combining. llvm-svn: 298914
* Wdocumentation fixSimon Pilgrim2017-03-281-1/+0
| | | | llvm-svn: 298911
* [X86][SSE] Set second operand to undef instead of first operand in unary ↵Simon Pilgrim2017-03-281-1/+2
| | | | | | | | shuffle combines. Copy isn't necessary after the matchVectorShuffleWithUNPCK refactor and undef value will make some future undef/zero handling easier. llvm-svn: 298910
* Strip trailing whitespaceSimon Pilgrim2017-03-281-1/+1
| | | | llvm-svn: 298909
* [AArch64] [Assembler] option to disable negative immediate conversionsSanne Wouda2017-03-286-10/+60
| | | | | | | | | | | | | | | | | Summary: Similar to the ARM target in https://reviews.llvm.org/rL298380, this patch adds identical infrastructure for disabling negative immediate conversions, and converts the existing aliases to the new infrastucture. Reviewers: rengolin, javed.absar, olista01, SjoerdMeijer, samparker Reviewed By: samparker Subscribers: samparker, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D31243 llvm-svn: 298908
* [GlobalISel][X86] support G_FRAME_INDEX instruction selection.Igor Breger2017-03-285-71/+201
| | | | | | | | | | | | | | | | Summary: G_LOAD/G_STORE, add alternative RegisterBank mapping. For G_LOAD, Fast and Greedy mode choose the same RegisterBank mapping (GprRegBank ) for the G_GLOAD + G_FADD , can't get rid of cross register bank copy GprRegBank->VecRegBank. Reviewers: zvi, rovka, qcolombet, ab Reviewed By: zvi Subscribers: llvm-commits, dberris, kristof.beyls, eladcohen, guyblank Differential Revision: https://reviews.llvm.org/D30979 llvm-svn: 298907
* [InstCombine] For select rule, use positive check of constant int for select ↵Anna Thomas2017-03-281-1/+1
| | | | | | operand. NFCI llvm-svn: 298906
* rename instcombine test file. NFCAnna Thomas2017-03-281-0/+0
| | | | llvm-svn: 298904
* [AMDGPU] Update SI scheduler colorHighLatenciesGroupsValery Pykhtin2017-03-282-22/+100
| | | | | | | | | | Depends on rL298896: MachineScheduler/ScheduleDAG: Add support for GetSubGraph Patch by Axel Davy (axel.davy@normalesup.org) Differential revision: https://reviews.llvm.org/D30152 llvm-svn: 298902
* Dont emit Mapping symbols for sections that contain only data.Weiming Zhao2017-03-2818-36/+177
| | | | | | | | | | | | | | | | | Summary: Dont emit mapping symbols for sections that contain only data. Patched by Shankar Easwaran <shankare@codeaurora.org> Reviewers: rengolin, peter.smith, weimingz, kparzysz, t.p.northover Reviewed By: t.p.northover Subscribers: t.p.northover, llvm-commits Differential Revision: https://reviews.llvm.org/D30724 llvm-svn: 298901
* [APInt] Reformat tc functions to put opening curly braces on the end of the ↵Craig Topper2017-03-281-104/+45
| | | | | | previous line. NFC llvm-svn: 298900
* [APInt] Remove an anonymous namespace around static functions. NFCCraig Topper2017-03-281-35/+33
| | | | llvm-svn: 298899
* [APInt] Combine variable declaration and initialization where possible in ↵Craig Topper2017-03-281-76/+36
| | | | | | the tc functions. NFCI llvm-svn: 298898
* [APInt] Use 'unsigned' instead of 'unsigned int' in the interface to the ↵Craig Topper2017-03-282-65/+62
| | | | | | APInt tc functions. This is more consistent with the rest of the codebase. NFC llvm-svn: 298897
* MachineScheduler/ScheduleDAG: Add support for GetSubGraphValery Pykhtin2017-03-282-0/+89
| | | | | | | | Patch by Axel Davy (axel.davy@normalesup.org) Differential revision: https://reviews.llvm.org/D30626 llvm-svn: 298896
* CodeGen : Check LLVM_ENABLE_DUMP definition for ↵Junmo Park2017-03-281-1/+2
| | | | | | | | | | | | | dumpMachineInstrRangeWithSlotIndex. Summary: Add missing check routine for dumpMachineInstrRangeWithSlotIndex including LLVM_DUMP_METHOD. Reviewers: bkramer Differential revision: https://reviews.llvm.org/D30367 llvm-svn: 298895
* [APInt] Move the single word cases of the bitwise operators inline.Craig Topper2017-03-282-21/+36
| | | | llvm-svn: 298894
* Revert "[asan] Delay creation of asan ctor."Alex Shlyapnikov2017-03-274-31/+23
| | | | | | | | Speculative revert. Some libfuzzer tests are affected. This reverts commit r298731. llvm-svn: 298890
* Revert "[asan] Put ctor/dtor in comdat."Alex Shlyapnikov2017-03-273-54/+10
| | | | | | | | Speculative revert, some libfuzzer tests are affected. This reverts commit r298756. llvm-svn: 298889
* Remove an oddly unnecessary temporary.Eric Christopher2017-03-271-2/+1
| | | | llvm-svn: 298888
* [ARM] Mark falky test unsupported until we find the causeRenato Golin2017-03-271-1/+1
| | | | llvm-svn: 298887
* [libfuzzer] Remove XFAIL for OutOfMemory test.Juergen Ributzka2017-03-271-1/+0
| | | | | | | | This test is now passing on Darwin. See rdar://problem/31282257. llvm-svn: 298886
* Improve machine schedulers for in-order processorsJaved Absar2017-03-277-1/+154
| | | | | | | | | | | This patch enables schedulers to specify instructions that cannot be issued with any other instructions. It also fixes BeginGroup/EndGroup. Reviewed by: Andrew Trick Differential Revision: https://reviews.llvm.org/D30744 llvm-svn: 298885
* Add the error handling for Mach-O dyld compact lazy bind, weak bind andKevin Enderby2017-03-2722-52/+351
| | | | | | | | | | | | | | | | | | | | | rebase entry errors and test cases for each of the error checks. Also verified with Nick Kledzik that a BIND_OPCODE_SET_ADDEND_SLEB opcode is legal in a lazy bind table, so code that had that as an error check was removed. With MachORebaseEntry and MachOBindEntry classes now returning an llvm::Error in all cases for malformed input the variables Malformed and logic to set use them is no longer needed and has been removed from those classes. Also in a few places, removed the redundant Done assignment to true when also calling moveToEnd() as it does that assignment. This only leaves the dyld compact export entries left to have error handling yet to be added for the dyld compact info. llvm-svn: 298883
* [LV] Transform truncations of non-primary induction variablesMatthew Simpson2017-03-272-11/+55
| | | | | | | | | | | | The vectorizer tries to replace truncations of induction variables with new induction variables having the smaller type. After r295063, this optimization was applied to all integer induction variables, including non-primary ones. When optimizing the truncation of a non-primary induction variable, we still need to transform the new induction so that it has the correct start value. This should fix PR32419. Reference: https://bugs.llvm.org/show_bug.cgi?id=32419 llvm-svn: 298882
* [APInt] Move operator=(uint64_t) inline as its pretty simple and is often ↵Craig Topper2017-03-272-11/+10
| | | | | | | | used with small constants that the compiler can optimize. While there recognize that we only need to clearUnusedBits on the single word case. llvm-svn: 298881
* [TableGen] Print #nnn as a name of an non-native reg unit with id nnnKrzysztof Parzyszek2017-03-272-6/+17
| | | | | | | | | When using -debug with -gen-register-info, tablegen will crash when trying to print a name of a non-native register unit. This patch only affects the debug information generated while running llvm-tblgen, and has no impact on the compilable code coming out of it. llvm-svn: 298875
* [AMDGPU] SISched: Detect dependency types between blocksValery Pykhtin2017-03-272-26/+39
| | | | | | | | Patch by Axel Davy (axel.davy@normalesup.org) Differential revision: https://reviews.llvm.org/D30153 llvm-svn: 298872
* [Support] Avoid concurrency hazard in signal handler registrationBruno Cardoso Lopes2017-03-271-5/+1
| | | | | | | | | | | | | | | | | | Several static functions from the signal API can be invoked simultaneously; RemoveFileOnSignal for instance can be called indirectly by multiple parallel loadModule() invocations, which might lead to the assertion: Assertion failed: (NumRegisteredSignals < array_lengthof(RegisteredSignalInfo) && "Out of space for signal handlers!"), function RegisterHandler, file /llvm/lib/Support/Unix/Signals.inc, line 105. RemoveFileOnSignal calls RegisterHandlers(), which isn't currently mutex protected, leading to the behavior above. This potentially affect a few other users of RegisterHandlers() too. rdar://problem/30381224 llvm-svn: 298871
* [APInt] Move operator&=(uint64_t) inline and use memset to clear the upper ↵Craig Topper2017-03-272-13/+9
| | | | | | | | words. This method is pretty new and probably isn't use much in the code base so this should have a negligible size impact. The OR and XOR operators are already inline. llvm-svn: 298870
* [GlobalISel][AArch64] Extract a variable out of an NDEBUG block. NFC.Ahmed Bougacha2017-03-271-2/+2
| | | | | | r298863 used PtrReg, but that's never defined in release builds. Fix it. llvm-svn: 298869
* [APInt] Use memset in setAllBits.Craig Topper2017-03-272-4/+40
| | | | llvm-svn: 298867
* Remove redundant check for nullptr.Adrian Prantl2017-03-271-2/+2
| | | | llvm-svn: 298866
* Remove unneccessary virtual destructor from DwarfExpression.Adrian Prantl2017-03-271-3/+3
| | | | llvm-svn: 298865
* [GlobalISel][AArch64] Fold FI into LDR/STR ui addressing mode.Ahmed Bougacha2017-03-273-0/+71
| | | | | | | | A majority of loads and stores at O0 access an alloca. It's trivial to fold the G_FRAME_INDEX into the instruction; do it. llvm-svn: 298864
* [GlobalISel][AArch64] Fold G_GEP into LDR/STR ui addressing mode.Ahmed Bougacha2017-03-273-1/+487
| | | | | | | | | | We're not to the point of supporting the load/store patterns yet (because they extensively use PatFrags). But in the meantime, we can implement some of the simplest addressing modes. llvm-svn: 298863
* [GlobalISel][AArch64] Select store of zero to WZR/XZR.Ahmed Bougacha2017-03-272-0/+67
| | | | | | These occur very frequently, and are quite trivial to catch. llvm-svn: 298862
* [AMDGPU] SISched: Update colorEndsAccordingToDependenciesValery Pykhtin2017-03-271-0/+14
| | | | | | | | Patch by Axel Davy (axel.davy@normalesup.org) Differential revision: https://reviews.llvm.org/D30150 llvm-svn: 298861
* [APInt] Move the >64 bit case for flipAllBits out of line.Craig Topper2017-03-272-5/+12
| | | | | | This is more consistent with what we do for other operations. This shrinks the opt binary on my build by ~72k. llvm-svn: 298858
* [AMDGPU] Fix SI scheduler LiveOut Refcount issueValery Pykhtin2017-03-272-0/+26
| | | | | | | | Patch by Axel Davy (axel.davy@normalesup.org) Differential revision: https://reviews.llvm.org/D30145 llvm-svn: 298857
* [GlobalISel][AArch64] Select CBZ.Ahmed Bougacha2017-03-273-3/+161
| | | | | | | | | | CBZ/CBNZ represent a substantial portion of all conditional branches. Look through G_ICMP to select them. We can't use tablegen yet because the existing patterns match an AArch64ISD node. llvm-svn: 298856
* [GlobalISel] Add a 'getConstantVRegVal' helper.Ahmed Bougacha2017-03-272-12/+24
| | | | | | Use it to compare immediate operands. llvm-svn: 298855
* [GlobalISel][AArch64] Use proper constant types in test. NFC.Ahmed Bougacha2017-03-271-2/+2
| | | | llvm-svn: 298854
* [AMDGPU][MC] Fix for Bug 28207 + LIT testsDmitry Preobrazhensky2017-03-276-18/+226
| | | | | | | | | | Enabled clamp and omod for v_cvt_* opcodes which have src0 of an integer type Reviewers: vpykhtin, arsenm Differential Revision: https://reviews.llvm.org/D31327 llvm-svn: 298852
* [AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as not having side effects.Chad Rosier2017-03-273-2/+72
| | | | | | | | | Among other things, this allows Machine LICM to hoist a costly 'mrs' instruction from within a loop. Differential Revision: http://reviews.llvm.org/D31151 llvm-svn: 298851
* [AMDGPU] Get address space mapping by target triple environmentYaxun Liu2017-03-2739-290/+446
| | | | | | | | | | | | | | | | | | As we introduced target triple environment amdgiz and amdgizcl, the address space values are no longer enums. We have to decide the value by target triple. The basic idea is to use struct AMDGPUAS to represent address space values. For address space values which are not depend on target triple, use static const members, so that they don't occupy extra memory space and is equivalent to a compile time constant. Since the struct is lightweight and cheap, it can be created on the fly at the point of usage. Or it can be added as member to a pass and created at the beginning of the run* function. Differential Revision: https://reviews.llvm.org/D31284 llvm-svn: 298846
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