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* Update the SplitAnalysis statistics as uses are moved from curli to the newJakob Stoklund Olesen2010-08-122-11/+44
| | | | | | | split intervals. THis means the analysis can be used for multiple splits as long as curli doesn't shrink. llvm-svn: 110975
* fix PR7876: If ipsccp decides that a function's address is takenChris Lattner2010-08-122-4/+43
| | | | | | before it rewrites the code, we need to use that in the post-rewrite pass. llvm-svn: 110962
* Some small clean-up: use of pseudo instructionsBruno Cardoso Lopes2010-08-121-24/+23
| | | | llvm-svn: 110954
* Cleaned up the for-disassembly-only entries in the arm instruction table so thatJohnny Chen2010-08-128-48/+74
| | | | | | | the memory barrier variants (other than 'SY' full system domain read and write) are treated as one instruction with option operand. llvm-svn: 110951
* Also recompute HasPHIKill flags in LiveInterval::RenumberValues.Jakob Stoklund Olesen2010-08-123-3/+25
| | | | | | | If a phi-def value were removed from the interval, the phi-kill flags are no longer valid. llvm-svn: 110949
* Make sure ARM constant island pass does not break up an IT block. If the ↵Evan Cheng2010-08-121-3/+20
| | | | | | split point is in the middle of an IT block, it should move it up to just above the IT instruction. rdar://8302637 llvm-svn: 110947
* - Teach SSEDomainFix to switch between different levels of AVX instructions. ↵Bruno Cardoso Lopes2010-08-123-27/+101
| | | | | | | | | | Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary. - Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too. - Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX. - Add a testcase for a simple 128-bit zero vector creation. llvm-svn: 110946
* Remove trailing whitespace.Jakob Stoklund Olesen2010-08-124-65/+65
| | | | llvm-svn: 110944
* Clean up debug output.Jakob Stoklund Olesen2010-08-122-34/+32
| | | | llvm-svn: 110940
* Define AVX 128-bit pattern versions of SET0PS/PD.Bruno Cardoso Lopes2010-08-122-6/+18
| | | | llvm-svn: 110937
* Add a test for llvm-gcc svn 110632.Bob Wilson2010-08-121-0/+16
| | | | llvm-svn: 110935
* Implement single block splitting.Jakob Stoklund Olesen2010-08-123-5/+158
| | | | | | | | | | Before spilling a live range, we split it into a separate range for each basic block where it is used. That way we only get one reload per basic block if the new smaller ranges can allocate to a register. This type of splitting is already present in the standard spiller. llvm-svn: 110934
* Optimize ScalarEvolution::getAddExpr's operand factoring code byDan Gohman2010-08-121-4/+7
| | | | | | | | having it finish processing all of the muliply operands before starting the whole getAddExpr process over again, instead of immediately after the first simplification. llvm-svn: 110916
* Hoist some loop-invariant code out of a hot loop.Dan Gohman2010-08-121-2/+4
| | | | llvm-svn: 110915
* Optimize ScalarEvolution::getAddExpr's duplicate operand detectionDan Gohman2010-08-121-3/+7
| | | | | | | | by having it finish processing the whole operand list before starting the whole getAddExpr process over again, instead of immediately after the first duplicate is found. llvm-svn: 110914
* Add a 'normalize' method to the Triple class, which takes a mucked upDuncan Sands2010-08-123-86/+322
| | | | | | | | | | | | | | | target triple and straightens it out. This does less than gcc's script config.sub, for example it turns i386-mingw32 into i386--mingw32 not i386-pc-mingw32, but it does a decent job of turning funky triples into something that the rest of the Triple class can understand. The plan is to use this to canonicalize triple's when they are first provided by users, and have the rest of LLVM only deal with canonical triples. Once this is done the special case workarounds in the Triple constructor can be removed, making the class more regular and easier to use. The comments and unittests for the Triple class are already adjusted in this patch appropriately for this brave new world of increased uniformity. llvm-svn: 110909
* Temporarily revert 110737 and 110734, they were causing failuresEric Christopher2010-08-122-170/+64
| | | | | | in an external testsuite. llvm-svn: 110905
* Fix comment orderBruno Cardoso Lopes2010-08-121-1/+1
| | | | llvm-svn: 110898
* Begin to support some vector operations for AVX 256-bit intructions. The longBruno Cardoso Lopes2010-08-124-19/+57
| | | | | | | | | term goal here is to be able to match enough of vector_shuffle and build_vector so all avx intrinsics which aren't mapped to their own built-ins but to shufflevector calls can be codegen'd. This is the first (baby) step, support building zeroed vectors. llvm-svn: 110897
* The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .tdJohnny Chen2010-08-123-0/+11
| | | | | | | | | | entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2. Recover by looking for ARM:USAT encoding pattern before delegating to the auto- gened decoder. Added a "usat" test case to arm-tests.txt. llvm-svn: 110894
* MC/X86/AsmParser: Give an explicit error message when we reject an instructionDaniel Dunbar2010-08-122-2/+36
| | | | | | because it could have an ambiguous suffix. llvm-svn: 110890
* MC/AsmParser: Push the burdon of emitting diagnostics about unmatchedDaniel Dunbar2010-08-124-23/+35
| | | | | | instructions onto the target specific parser, which can do a better job. llvm-svn: 110889
* tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl',Daniel Dunbar2010-08-124-13/+11
| | | | | | target specific parsers can adapt the TargetAsmParser to this. llvm-svn: 110888
* This is x86 only test.Devang Patel2010-08-121-1/+1
| | | | llvm-svn: 110887
* configure: Add detection of the linker version string.Daniel Dunbar2010-08-114-1/+53
| | | | | | | - Review appreciated, as long as you understand that I understand that this is a horrible hack. llvm-svn: 110883
* Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.Johnny Chen2010-08-114-9/+12
| | | | | | Added two test cases to arm-tests.txt. llvm-svn: 110880
* Even if a variable has constant value all the time, it is still a variable ↵Devang Patel2010-08-111-1/+1
| | | | | | | | in gdb's eyes. Tested by scope.exp in gdb testsuite. llvm-svn: 110876
* Move the ARM SSAT and USAT optional shift amount operand out of theBob Wilson2010-08-119-44/+80
| | | | | | instruction opcode. This also fixes part of PR7792. llvm-svn: 110875
* Fix <rdar://problem/8282498> even if it doesn't reproduce on trunk.Jakob Stoklund Olesen2010-08-111-0/+5
| | | | | | | | | | | | | | When a register is defined by a partial load: %reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234 That load cannot be folded into an instruction using the full 64-bit register. It would become a 64-bit load. This is related to the recent change to have isLoadFromStackSlot return false on a sub-register load. llvm-svn: 110874
* Fix a subtle use-after-free issue.Owen Anderson2010-08-111-1/+4
| | | | llvm-svn: 110863
* Clean up ConstantRange a bit:Nick Lewycky2010-08-113-98/+127
| | | | | | | | | - remove ashr which never worked. - fix lshr and shl and add tests. - remove dead function "intersect1Wrapped". - add a new sub method to subtract ranges, with test. llvm-svn: 110861
* Add testcases for all AVX 256-bit intrinsics added in the last couple daysBruno Cardoso Lopes2010-08-111-0/+751
| | | | llvm-svn: 110854
* Make LoopPass::getContainedPass return a LoopPass* instead of a Pass*Dan Gohman2010-08-112-8/+8
| | | | | | and remove casts from all its callers. llvm-svn: 110848
* Remove BasicBlockPass::runOnFunction, which was unused.Dan Gohman2010-08-112-16/+0
| | | | llvm-svn: 110847
* Remove rsqrt/sqrt_nr intrinsics since there are no more builtins for them on ↵Bruno Cardoso Lopes2010-08-111-5/+0
| | | | | | clang llvm-svn: 110845
* Delete FunctionPass::run, which is unused.Dan Gohman2010-08-112-16/+0
| | | | llvm-svn: 110843
* Delete FunctionPass::runOnModule, which is unused.Dan Gohman2010-08-112-19/+0
| | | | llvm-svn: 110842
* Don't use unsigned char for alignments in TargetData. There aren'tDan Gohman2010-08-112-34/+34
| | | | | | | | that many of these things, so the memory savings isn't significant, and there are now situations where there can be alignments greater than 128. llvm-svn: 110836
* Use ISD::ADD instead of ISD::SUB with a negated constant. ThisDan Gohman2010-08-111-4/+5
| | | | | | | | | | | avoids trouble if the return type of TD->getPointerSize() is changed to something which doesn't promote to a signed type, and is simpler anyway. Also, use getCopyFromReg instead of getRegister to read a physical register's value. llvm-svn: 110835
* Reapply r109881 using a more strict command line for llc.Bruno Cardoso Lopes2010-08-112-0/+2006
| | | | llvm-svn: 110833
* fix silly typoJim Grosbach2010-08-111-2/+2
| | | | llvm-svn: 110831
* Add a target triple, as the runtime library invocation varies a bit byJim Grosbach2010-08-111-3/+3
| | | | | | | | | platform. It's apparently "bl __muldf3" on linux, for example. Since that's not what we're checking here, it's more robust to just force a triple. We just wwant to check that the inline FP instructions are only generated on cpus that have them." llvm-svn: 110830
* Fix test and re-enable it.Evan Cheng2010-08-111-4/+4
| | | | llvm-svn: 110829
* Fix a FIXME. The SlotIndex::Slot enum should be private.Jakob Stoklund Olesen2010-08-112-16/+30
| | | | llvm-svn: 110826
* Temporarily disable some failing tests, until they can beDan Gohman2010-08-111-2/+2
| | | | | | properly investigated. llvm-svn: 110825
* cortex m4 has floating point support, but only single precision.Jim Grosbach2010-08-115-2/+35
| | | | llvm-svn: 110810
* Temporarily disable some failing tests, until they can beDan Gohman2010-08-111-2/+2
| | | | | | properly investigated. llvm-svn: 110808
* Consider this code snippet:Bill Wendling2010-08-113-3/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | float t1(int argc) { return (argc == 1123) ? 1.234f : 2.38213f; } We would generate truly awful code on ARM (those with a weak stomach should look away): _t1: movw r1, #1123 movs r2, #1 movs r3, #0 cmp r0, r1 mov.w r0, #0 it eq moveq r0, r2 movs r1, #4 cmp r0, #0 it ne movne r3, r1 adr r0, #LCPI1_0 ldr r0, [r0, r3] bx lr The problem was that legalization was creating a cascade of SELECT_CC nodes, for for the comparison of "argc == 1123" which was fed into a SELECT node for the ?: statement which was itself converted to a SELECT_CC node. This is because the ARM back-end doesn't have custom lowering for SELECT nodes, so it used the default "Expand". I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this testcase, but can obviously be expanded to include more cases. Now we generate this, which looks optimal to me: _t1: movw r1, #1123 movs r2, #0 cmp r0, r1 adr r0, #LCPI0_0 it eq moveq r2, #4 ldr r0, [r0, r2] bx lr .align 2 LCPI0_0: .long 1075344593 @ float 2.382130e+00 .long 1067316150 @ float 1.234000e+00 llvm-svn: 110799
* Report error if codegen tries to instantiate a ARM target when the cpu does ↵Evan Cheng2010-08-116-13/+15
| | | | | | support it. e.g. cortex-m* processors. llvm-svn: 110798
* ArchV7M implies HW division instructions.Evan Cheng2010-08-111-3/+3
| | | | llvm-svn: 110797
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