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* Fix PR31896.Evgeniy Stepanov2017-02-212-5/+24
| | | | | | Address of an alias of a global with offset is incorrectly lowered as an address of the global (i.e. ignoring offset). llvm-svn: 295762
* Try to fix line endings.Zachary Turner2017-02-212-640/+640
| | | | llvm-svn: 295759
* [InstCombine] canonicalize non-obivous forms of integer min/maxSanjay Patel2017-02-213-39/+37
| | | | | | | | | | | | | | | | This is part of trying to clean up our handling of min/max patterns in IR. By converting these to canonical form, we're more likely to recognize them because there are various places in InstCombine that don't use matchSelectPattern or m_SMax and friends. The backend fixups referenced in the now deleted TODO comment were added with: https://reviews.llvm.org/rL291392 https://reviews.llvm.org/rL289738 If there's any codegen fallout from this change, we should be able to address it in DAGCombiner or target-specific lowering. llvm-svn: 295758
* AMDGPU: Remove dead declarations in testsMatt Arsenault2017-02-212-8/+0
| | | | llvm-svn: 295757
* Remove svn:eol-style property from 2 files.Zachary Turner2017-02-212-640/+640
| | | | | | There are still over 3400 files remaining with this property set, but there are tens of thousands more with the property not set. Until we decide what to do on a global scale, this at least unblocks me temporarily. llvm-svn: 295756
* AMDGPU: Remove dead declarations from MIR testsMatt Arsenault2017-02-213-48/+5
| | | | llvm-svn: 295755
* AMDGPU: Remove llvm.AMDGPU.flbit intrinsicMatt Arsenault2017-02-213-29/+0
| | | | llvm-svn: 295754
* AMDGPU: Don't use stack space for SGPR->VGPR spillsMatt Arsenault2017-02-2111-94/+876
| | | | | | | | | | | | | | | | Before frame offsets are calculated, try to eliminate the frame indexes used by SGPR spills. Then we can delete them after. I think for now we can be sure that no other instruction will be re-using the same frame indexes. It should be easy to notice if this assumption ever breaks since everything asserts if it tries to use a dead frame index later. The unused emergency stack slot seems to still be left behind, so an additional 4 bytes is still wasted. llvm-svn: 295753
* [LoopSimplify] Simplify how we compute UniqueExitXin Tong2017-02-211-8/+1
| | | | | | | | | | | | Summary: Simplify how we compute UniqueExit. Reuse ExitBlockSet. Reviewers: sanjoy, efriedma, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30182 llvm-svn: 295751
* More comments for getUniqueExitBlocks. NFCIXin Tong2017-02-211-1/+2
| | | | llvm-svn: 295750
* Teach the IR verifier to reject conflicting debug info for function arguments.Adrian Prantl2017-02-212-0/+64
| | | | | | | | | | | Conflicting debug info for function arguments causes hard-to-debug assertions in the DWARF backend, so the Verifier should reject it. For performance reasons this only checks function arguments from non-inlined debug intrinsics for now. rdar://problem/30520286 llvm-svn: 295749
* [CodeGenPrepare] Sink and duplicate more 'and' instructions.Geoff Berry2017-02-2110-91/+403
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Rework the code that was sinking/duplicating (icmp and, 0) sequences into blocks where they were being used by conditional branches to form more tbz instructions on AArch64. The new code is more general in that it just looks for 'and's that have all icmp 0's as users, with a target hook used to select which subset of 'and' instructions to consider. This change also enables 'and' sinking for X86, where it is more widely beneficial than on AArch64. The 'and' sinking/duplicating code is moved into the optimizeInst phase of CodeGenPrepare, where it can take advantage of the fact the OptimizeCmpExpression has already sunk/duplicated any icmps into the blocks where they are used. One minor complication from this change is that optimizeLoadExt needed to be updated to always mark 'and's it has determined should be in the same block as their feeding load in the InsertedInsts set to avoid an infinite loop of hoisting and sinking the same 'and'. This change fixes a regression on X86 in the tsan runtime caused by moving GVNHoist to a later place in the optimization pipeline (see PR31382). Reviewers: t.p.northover, qcolombet, MatzeB Subscribers: aemerson, mcrosier, sebpop, llvm-commits Differential Revision: https://reviews.llvm.org/D28813 llvm-svn: 295746
* AMDGPU : AMDGPU : Update AMDGPU Trap Handler ABI.Wei Ding2017-02-211-41/+49
| | | | | | Differential Revision: http://reviews.llvm.org/D29913 llvm-svn: 295745
* Test commitDmitry Preobrazhensky2017-02-212-0/+4
| | | | llvm-svn: 295740
* [X86] EltsFromConsecutiveLoads SDLoc argument should be const&.Simon Pilgrim2017-02-211-1/+1
| | | | | | There appears never to have been a time that the reference was updated. llvm-svn: 295739
* Do not leak OpenedHandles.Vassil Vassilev2017-02-212-7/+4
| | | | | | Reviewed by Vedant Kumar (D30178) llvm-svn: 295737
* [X86][AVX512] Update VPBROADCASTQ test to combine from VPERMQ instead of ↵Simon Pilgrim2017-02-211-7/+6
| | | | | | | | VPERMI2Q. VPERMI2Q doesn't have shuffle decoding from re-materializable constants. llvm-svn: 295736
* [X86][AVX] Rename shuffle combine tests to show combined shuffle type. NFCI.Simon Pilgrim2017-02-212-9/+9
| | | | llvm-svn: 295735
* [ARM] Correct SP/PC handling in t2MOVrJohn Brawn2017-02-211-0/+100
| | | | | | Add a missing test that I forgot to svn add in my previous commit llvm-svn: 295734
* [X86][AVX2] Fix VPBROADCASTQ folding on 32-bit targets.Simon Pilgrim2017-02-213-4/+18
| | | | | | As i64 isn't a value type on 32-bit targets, we need to fold the VZEXT_LOAD into VPBROADCASTQ. llvm-svn: 295733
* [ARM] Correct SP/PC handling in t2MOVrJohn Brawn2017-02-212-4/+20
| | | | | | | | | | PC isn't allowed in the source operand of t2MOVr, so change the register class to one without PC. SP handling is slightly trickier and changes depending on if we're in ARMv8, so do that in checkTargetMatchPredicate. Differential Revision: https://reviews.llvm.org/D30199 llvm-svn: 295732
* [X86][AVX2] Add AVX512 test targets to AVX2 shuffle combines.Simon Pilgrim2017-02-211-24/+50
| | | | llvm-svn: 295731
* [X86][AVX] Add tests showing missed VPBROADCASTQ folding on 32-bit targets.Simon Pilgrim2017-02-212-0/+54
| | | | | | | | As i64 isn't a value type on 32-bit targets, we fail to fold the VZEXT_LOAD into VPBROADCASTQ. Also shows that we're not decoding VPERMIV3 shuffles very well.... llvm-svn: 295729
* [X86][SSE] Prefer to combine shuffles to VZEXT over VZEXT_MOVL.Simon Pilgrim2017-02-212-29/+14
| | | | | | This matches what is already done during shuffle lowering and helps prevent the need for a zero-vector in cases where shuffles match both patterns. llvm-svn: 295723
* [X86][SSE] Added SSE41 shuffle combining test file.Simon Pilgrim2017-02-211-0/+38
| | | | | | Currently just contains one case where we combine to VZEXT_MOVL instead of VZEXT which would avoid the need for a zero vector to be generated llvm-svn: 295721
* [InstCombine] Do not exercise nested max/min pattern on absAnna Thomas2017-02-212-1/+25
| | | | | | | | | | | | | | | | | | | Summary: This is a fix for assertion failure in `getInverseMinMaxSelectPattern` when ABS is passed in as a select pattern. We should not be invoking the simplification rule for ABS(MIN(~ x,y))) or ABS(MAX(~x,y)) combinations. Added a test case which would cause an assertion failure without the patch. Reviewers: sanjoy, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30051 llvm-svn: 295719
* [AVX512] Fix EXTRACT_VECTOR_ELT for v2i1/v4i1/v32i1/v64i1 with variable index.Igor Breger2017-02-213-3/+266
| | | | | | Differential Revision: https://reviews.llvm.org/D30189 llvm-svn: 295718
* [SLP] Tests for shuffle/blending operations.Alexey Bataev2017-02-211-0/+167
| | | | llvm-svn: 295717
* [ARM] GlobalISel: Lower calls to void() functionsDiana Picus2017-02-213-0/+62
| | | | | | | For now, we hardcode a BLX instruction, and generate an ADJCALLSTACKDOWN/UP pair with amount 0. llvm-svn: 295716
* tablegen: Fix android buildPavel Labath2017-02-211-1/+2
| | | | | | use llvm::to_string instead of std:: version. llvm-svn: 295711
* [X86] Remove ssse3 intrinsic tests from the avx intrinsics test file.Craig Topper2017-02-212-220/+33
| | | | | | They are all covered by the SSSE3 intrinsics test with SSSE3, AVX, and AVX512 command lines. llvm-svn: 295708
* [X86] Remove sse4.2 intrinsic tests from the avx intrinsics test file. Fix ↵Craig Topper2017-02-215-402/+69
| | | | | | | | | | some other consistency issues. They are all covered by the SSE4.2 intrinsics test with SSE4.2, AVX, and AVX512 command lines. Merge sse42.ll into the other intrinsics test. Rename sse42_64.ll to be named like other intrinsic tests. llvm-svn: 295707
* [X86] Remove sse4.1 intrinsic tests from the avx intrinsics test file.Craig Topper2017-02-211-343/+4
| | | | | | They are all covered by the SSE4.1 intrinsics test with SSE4.1, AVX, and AVX512 command lines. llvm-svn: 295706
* [X86] Remove sse3 intrinsic tests from the avx intrinsics test file.Craig Topper2017-02-212-113/+35
| | | | | | They are all covered by the SSE3 intrinsics test with SSE2, AVX, and AVX512 command lines. llvm-svn: 295705
* The patch introduces new way of narrowing complex (>UINT16 variants) solutions.Evgeny Stupachenko2017-02-213-3/+161
| | | | | | | | | | | | | | | | | | | The new method introduced under "-lsr-exp-narrow" option (currenlty set to true). Summary: The method is based on registers number mathematical expectation and should be generally closer to optimal solution. Please see details in comments to "LSRInstance::NarrowSearchSpaceByDeletingCostlyFormulas()" function (in lib/Transforms/Scalar/LoopStrengthReduce.cpp). Reviewers: qcolombet Differential Revision: http://reviews.llvm.org/D29862 From: Evgeny Stupachenko <evstupac@gmail.com> llvm-svn: 295704
* [X86] Remove aes intrinsic tests from the avx intrinsics test file.Craig Topper2017-02-211-71/+4
| | | | | | They are all covered by the AES intrinsics test with a legacy command line and an AVX command line. llvm-svn: 295702
* [X86] Add an AVX command line and regenerate AES intrinsics test using the ↵Craig Topper2017-02-211-7/+57
| | | | | | update_llc_test_checks.py llvm-svn: 295701
* [X86] Remove sse2 intrinsic tests from the avx intrinsics test file.Craig Topper2017-02-215-1223/+113
| | | | | | | | They are all covered by the SSE2 intrinsics test with SSE2, AVX, and AVX512 command lines. Also remove an unneeded lfence intrinsic test since it was already covered. llvm-svn: 295700
* [X86] Remove sse1 intrinsic tests from the avx intrinsics test file.Craig Topper2017-02-215-549/+98
| | | | | | | | They are all covered by the SSE intrinsics test with SSE, AVX, and AVX512 command lines. Also remove an unneeded sfence intrinsic test since it was already covered. llvm-svn: 295699
* [X86] Use SHLD with both inputs from the same register to implement rotate ↵Craig Topper2017-02-217-1/+44
| | | | | | | | | | | | | | | | | | | on Sandy Bridge and later Intel CPUs Summary: Sandy Bridge and later CPUs have better throughput using a SHLD to implement rotate versus the normal rotate instructions. Additionally it saves one uop and avoids a partial flag update dependency. This patch implements this change on any Sandy Bridge or later processor without BMI2 instructions. With BMI2 we will use RORX as we currently do. Reviewers: zvi Reviewed By: zvi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30181 llvm-svn: 295697
* [X86] Fix formatting. NFCCraig Topper2017-02-211-1/+1
| | | | llvm-svn: 295695
* [AVX-512] Use sse_load_f32/f64 in place of scalar_to_vector and scalar load ↵Craig Topper2017-02-212-23/+22
| | | | | | in some patterns. llvm-svn: 295693
* [AVX-512] Add test cases showing failure to fold zero extending scalar loads ↵Craig Topper2017-02-211-0/+77
| | | | | | in scalar intrinsics without the peephole pass. llvm-svn: 295692
* [AVX-512] Fix the ExeDomain for vcmpss/vcmpsd.Craig Topper2017-02-211-0/+2
| | | | llvm-svn: 295691
* [ValueTracking] clang-format a section I'm about to touch; NFCSanjoy Das2017-02-211-64/+64
| | | | | | (Whitespace only change) llvm-svn: 295690
* ScheduleDAG: Cleanup; NFCMatthias Braun2017-02-212-393/+322
| | | | | | | | | - Fix doxygen comments (do not repeat documented name, remove definition comment if there is already one at the declaration, add \p, ...) - Add some const modifiers - Use range based for llvm-svn: 295688
* SubtargetFeature: Cleanup; NFCMatthias Braun2017-02-212-104/+65
| | | | | | | | | - Fix doxygen comments - Remove duplicated comments - Remove section comments (which became wrong over time) - Use more `const` and references but less `auto` llvm-svn: 295687
* Add a wrapper around copy_if in STLExtras; NFCSanjoy Das2017-02-216-46/+48
| | | | | | I will add one more use for this in a later change. llvm-svn: 295685
* [BranchFolding] Update debug location along with the update of branch ↵Taewook Oh2017-02-212-3/+86
| | | | | | | | | | | | | | | | | | | | | | | instruction. Summary: Currently, BranchFolder drops DebugLoc for branch instructions in some places. For example, for the test code attached, the branch instruction of 'entry' block has a DILocation of ``` !12 = !DILocation(line: 6, column: 3, scope: !11) ``` , but this information is gone when then block is lowered because BranchFolder misses it. This patch is a fix for this issue. Reviewers: qcolombet, aprantl, craig.topper, MatzeB Reviewed By: aprantl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29902 llvm-svn: 295684
* [X86] Add additonal check lines to one of the rotate tests.Craig Topper2017-02-201-1/+3
| | | | llvm-svn: 295682
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