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* ARMEB: Fix byte order of EH frame unwinding instructions, with modified test ↵Christian Pirker2014-05-132-4/+87
| | | | | | | | | | | | file This commit was already commited as revision rL208689 and discussd in phabricator revision D3704. But the test file was crashing on OS X and windows. I fixed the test file in the same way as in rL208340. llvm-svn: 208711
* Style fix: The name of variables starts with an upper case letter.Rafael Espindola2014-05-131-3/+3
| | | | llvm-svn: 208710
* Revert "autoconf: Fix soname for libLLVM-Major.Minor.so"Tom Stellard2014-05-131-2/+2
| | | | | | | | | This reverts commit r208708. I forgot to run make clean before testing this and it broke tools linking. llvm-svn: 208709
* autoconf: Fix soname for libLLVM-Major.Minor.soTom Stellard2014-05-131-2/+2
| | | | | | | | | | | | | We were using libLLVM-Major.Minor.Patch.so for the soname, but we need the soname to stay consistent for all Major.Minor.* releases otherwise operating system distributors will need to rebuild all packages that link with LLVM every time there is a new point release. This patch also reverses the compatibility symlink, so libLLVM-Major.Minor.Patch.so is now a symlink that points to libLLVM-Major-Minor.so. llvm-svn: 208708
* [CGP] r205941 changed the logic, so that a cast happens *before* 'Result' isJoey Gouly2014-05-132-1/+15
| | | | | | | | | | | compared to 'AddrMode.BaseReg'. In the case that 'AddrMode.BaseReg' is nullptr, 'Result' will also be nullptr, so the cast causes an assertion. We should use dyn_cast_or_null here to check 'Result' is not null and it is an instruction. Bug found by Mats Petersson, and I reduced his IR to get a test case. llvm-svn: 208705
* Revert "ARMEB: Fix byte order of EH frame unwinding instructions"Rafael Espindola2014-05-132-87/+4
| | | | | | | | This reverts commit r208689. The test was crashing on OS X and windows. llvm-svn: 208704
* Teach the table generator to not generate switch statements containing only ↵Aaron Ballman2014-05-131-12/+15
| | | | | | | | a default label with no cases. This solves some warnings with MSVC. No functional changes intended. llvm-svn: 208694
* ARM: Additional test files for thumb fixupsChristian Pirker2014-05-133-0/+36
| | | | llvm-svn: 208691
* [mips] Marked up instructions added in MIPS32r2 and tested that IAS for ↵Daniel Sanders2014-05-1316-42/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | -mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 llvm-svn: 208690
* ARMEB: Fix byte order of EH frame unwinding instructionsChristian Pirker2014-05-132-4/+87
| | | | llvm-svn: 208689
* [mips] Free up two values in SubtargetFeatureFlag by folding the redundant ↵Daniel Sanders2014-05-132-6/+5
| | | | | | | | | | | | | | | | | | | | | IsGP32/IsGP64 into IsGP32bit/IsGP64bit Summary: We are currently very close to the 32-bit limit of the current assembler implementation. This is because there is no way to represent an instruction that is available in, for example, Mips3 or Mips32. We have to define a feature bit that represents this. This patch cleans up a pair of redundant feature bits and slightly postpones the point we will reach the limit. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3703 llvm-svn: 208685
* Fix build failure with MSVC, following r208680Artyom Skrobov2014-05-131-2/+3
| | | | llvm-svn: 208684
* include/llvm/Support/Unicode.h didn't have re-include guardsArtyom Skrobov2014-05-131-0/+5
| | | | llvm-svn: 208681
* [un]wrap extracted from lib/Target/Target[MachineC].cpp, ↵Artyom Skrobov2014-05-134-33/+10
| | | | | | lib/ExecutionEngine/ExecutionEngineBindings.cpp into include/llvm/IR/DataLayout.h llvm-svn: 208680
* TableGen: strengthen assertTim Northover2014-05-131-1/+1
| | | | llvm-svn: 208679
* Fix gcc -Wparentheses warning.Jay Foad2014-05-131-1/+2
| | | | llvm-svn: 208675
* [ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg ↵Kevin Qin2014-05-133-13/+48
| | | | | | | | | addressing mode. A vague diagnostic replaced the misleading one. This can fix bug 19502. llvm-svn: 208669
* Fix type of shuffle resulted from shuffle merge.Serge Pavlov2014-05-132-6/+12
| | | | | | This fix resolves PR19730. llvm-svn: 208666
* Assert that we don't RAUW a Constant with a ConstantExpr that contains it.Rafael Espindola2014-05-132-1/+53
| | | | | | | | We already had an assert for foo->RAUW(foo), but not for something like foo->RAUW(GEP(foo)) and would go in an infinite loop trying to apply the replacement. llvm-svn: 208663
* Folding into CSEL when there is ZEXT between SETCC and ADDWeiming Zhao2014-05-132-3/+22
| | | | | | | | | | | Normally, patterns like (add x, (setcc cc ...)) will be folded into (csel x, x+1, not cc). However, if there is a ZEXT after SETCC, they won't be folded. This patch recognizes the ZEXT and allows the generation of CSINC. This patch fixes bug 19680. llvm-svn: 208660
* Convert test to FileCheck.Rafael Espindola2014-05-131-1/+8
| | | | llvm-svn: 208658
* Convert test to FileCheck.Rafael Espindola2014-05-131-2/+12
| | | | llvm-svn: 208644
* Revert "DebugInfo: Include lexical scopes in inlined subroutines."David Blaikie2014-05-125-130/+21
| | | | | | | | | This reverts commit r208506. Some inlined subroutine scopes appear to be missing with this change. Reverting while I investigate. llvm-svn: 208642
* Use a logical not when inverting SetCC. This unfortunately doesn't fire on ↵Pete Cooper2014-05-123-3/+22
| | | | | | | | | | | | any targets so I couldn't find a test case to trigger it. The problem occurs when a non-i1 setcc is inverted. For example 'i8 = setcc' will get 'xor 0xff' to invert this. This is clearly wrong when the boolean contents are ZeroOrOne. This patch introduces getLogicalNOT and updates SetCC legalisation to use it. Reviewed by Hal Finkel. llvm-svn: 208641
* [DAGCombiner] Split up an indexed load if only the base pointer value is liveAdam Nemet2014-05-122-7/+59
| | | | | | | | | | | | | | | | | | | | Right now the load may not get DCE'd because of the side-effect of updating the base pointer. This can happen if we lower a read-modify-write of an illegal larger type (e.g. i48) such that the modification only affects one of the subparts (the lower i32 part but not the higher i16 part). See the testcase. In order to spot the dead load we need to revisit it when SimplifyDemandedBits decided that the value of the load is masked off. This is the CommitTargetLoweringOpt piece. I checked compile time with ARM64 by sending SPEC bitcode files through llc. No measurable change. Fixes <rdar://problem/16031651> llvm-svn: 208640
* Fix ARM bswap16.ll test on WindowsLouis Gerbarg2014-05-121-2/+2
| | | | | | | Windows on ARM only supports thumb mode execution, so we have to explicitly pick some non-Windows OS to test ARM mode codegen. llvm-svn: 208638
* Try to fix an SDAG dependence issue with sretReid Kleckner2014-05-123-18/+41
| | | | | | | | | | | | | | | | r208453 added support for having sret on the second parameter. In that change, the code for copying sret into a virtual register was hoisted into the loop that lowers formal parameters. This caused a "Wrong topological sorting" assertion failure during scheduling when a parameter is passed in memory. This change undoes that by creating a second loop that deals with sret. I'm worried that this fix is incomplete. I don't fully understand the dependence issues. However, with this change we produce the same DAGs we used to produce, so if they are broken, they are just as broken as they have always been. llvm-svn: 208637
* DebugInfo: Attach DW_AT_inline to inlined subprograms at DIE-construction ↵David Blaikie2014-05-121-4/+1
| | | | | | time rather than as a post-processing step. llvm-svn: 208636
* [RuntimeDyld] Add support for MachO __jump_table and __pointers sections, andLang Hames2014-05-128-23/+245
| | | | | | | | | | | SECTDIFF relocations on 32-bit x86. This fixes several of the MCJIT regression test failures that show up on 32-bit builds. <rdar://problem/16886294> llvm-svn: 208635
* DebugInfo: Make gmlt debug info more gmlt-like by removing variables.David Blaikie2014-05-121-6/+1
| | | | | | | | | | | For some impending improvements to debug info, LLVM will start assuming that when the CU specifies llvm::DIBuilder::LineTablesOnly, the IR for functions described by that CU will not include variables, types, etc. (might be worth having some test coverage for GMLT + non-GMLT CUs, especially with non-GMLT functions inlined into GMLT CU functions) llvm-svn: 208634
* Suggested improvement by Rafael Espindola to use isa<> in a few placesKevin Enderby2014-05-121-6/+6
| | | | | | instead of dyn_cast<>. llvm-svn: 208628
* Use cast<> for unchecked useMatt Arsenault2014-05-121-1/+1
| | | | llvm-svn: 208627
* use nullptr instead of NULLSebastian Pop2014-05-121-4/+4
| | | | llvm-svn: 208622
* [Test] Trim unnecessary .c and .cpp from config.suffix in lit.local.cfgAdam Nemet2014-05-127-7/+7
| | | | | | | | | | | | | | Tested by comparing make check VERBOSE=1 before and after to make sure no tests are missed. (VERBOSE=1 prints the list of tests.) Only one test :( remains where .cpp is required: tools/llvm-cov/range_based_for.cpp:// RUN: llvm-cov range_based_for.cpp | FileCheck %s --check-prefix=STDOUT The topic was discussed in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140428/214905.html llvm-svn: 208621
* Add support bswap16 to/from memory compiling to rev16 on ARM/ThumbLouis Gerbarg2014-05-123-0/+59
| | | | | | | | | | | The current patterns for REV16 misses mostn __builtin_bswap16() due to legalization promoting the operands to from load/stores toi32s and then truncing/extending them. This patch adds new patterns that catch the resultant DAGs and codegens them to rev16 instructions. Tests included. rdar://15353652 llvm-svn: 208620
* Use cast<> for unchecked useMatt Arsenault2014-05-121-2/+2
| | | | llvm-svn: 208618
* Use range forMatt Arsenault2014-05-122-6/+4
| | | | llvm-svn: 208617
* do not assert when delinearization failsSebastian Pop2014-05-122-8/+73
| | | | llvm-svn: 208615
* use isZero()Sebastian Pop2014-05-121-6/+5
| | | | llvm-svn: 208614
* DwarfDebug: Avoid an extra map lookup while constructing abstract scope DIEs ↵David Blaikie2014-05-122-21/+21
| | | | | | | | | | and reduce nesting/conditionals. One test case had to be updated as it still had the extra indirection for the variable list - removing the extra indirection got it back to passing. llvm-svn: 208608
* TableGen: use PrintMethods to print more aliasesTim Northover2014-05-1238-309/+464
| | | | llvm-svn: 208607
* AArch64/ARM64: use InstAliases for NEON logical (imm) instructions.Tim Northover2014-05-122-72/+67
| | | | llvm-svn: 208606
* AArch64/ARM64: implement "mov $Rd, $Imm" aliases in TableGen.Tim Northover2014-05-123-58/+94
| | | | | | | | This is a slightly different approach to AArch64 (the base instruction definitions aren't quite right for that to work), but achieves the same thing and reduces C++ hackery in AsmParser. llvm-svn: 208605
* R600: Add mul24 intrinsicsMatt Arsenault2014-05-125-4/+35
| | | | llvm-svn: 208604
* Make SimplifyDemandedBits understand BUILD_PAIRMatt Arsenault2014-05-122-0/+61
| | | | llvm-svn: 208598
* [mips] Move disassembler test (test_2r_msa64) into correct folder.Matheus Almeida2014-05-122-6/+3
| | | | llvm-svn: 208594
* [mips] Move disassembler test (Mips MSA test_vec) into correct folder.Matheus Almeida2014-05-122-12/+9
| | | | llvm-svn: 208592
* [mips] Move disassembler tests (Mips MSA test_i*, test_mi10) into correct ↵Matheus Almeida2014-05-128-105/+92
| | | | | | folder. llvm-svn: 208590
* [mips] Move disassembler tests (Mips MSA test_elm*) into correct folder.Matheus Almeida2014-05-1210-50/+37
| | | | llvm-svn: 208589
* [mips] Move disassembler tests (Mips MSA test_lsa, test_dlsa) into correct ↵Matheus Almeida2014-05-124-18/+12
| | | | | | folder. llvm-svn: 208588
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