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* [Asm] Improve "too few operands" errorsOliver Stannard2017-11-216-12/+37
| | | | | | | | | | - We can still emit this error if the actual instruction has two or more operands missing compared to the expected one. - We should only emit this error once per instruction. Differential revision: https://reviews.llvm.org/D36746 llvm-svn: 318770
* [Asm] Finish matching once end of formal and actual lists reached (NFC)Oliver Stannard2017-11-211-0/+1
| | | | | | | | | | This is NFC, as the matcher would continue looping up to the maximum number of operands with no effect, but this should improve performance a bit, and makes the debug trace clearer. Differential revision: https://reviews.llvm.org/D36744 llvm-svn: 318769
* Revert r318759 due to make check-all failure on WindowsSander de Smalen2017-11-213-17/+18
| | | | llvm-svn: 318768
* [ARM] Add diagnostics for SPR/DPR listsOliver Stannard2017-11-213-2/+55
| | | | | | Differential revision: https://reviews.llvm.org/D39195 llvm-svn: 318766
* [InstCombine] Test for PR35354: unable to vectorize loop with std::maxAlexey Bataev2017-11-211-0/+57
| | | | | | on floats, NFC. llvm-svn: 318764
* [AMDGPU] SDWA: remove omod src operand for VOP2b instructionsSam Kolton2017-11-212-0/+35
| | | | | | | | | | | | Summary: VOP2b instructions (v_subbrev_u32, v_add_i32 ...) shouldn't support OMod operand in SDWA encoding Reviewers: rampitec, dp Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D40172 llvm-svn: 318761
* [RISCV][NFC] Remove unnecessary {} around single statement if blockAlex Bradbury2017-11-211-2/+1
| | | | | | | Almost too trivial to worry about, but it seems worth having consistency with upcoming commits. llvm-svn: 318760
* [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand.Sander de Smalen2017-11-213-18/+17
| | | | | | | | | | | | | | | | | Summary: The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand. This is because the code will only update the diagnostic if it is more specific than the previous diagnostic. However, when having validated operands and 'moved on' to a next operand (for some instruction/alias for which all previous operands are valid), if the diagnostic is InvalidOperand, than that should be set as the diagnostic, not the more specific message about a previous operand for some other instruction/alias candidate. Reviewers: craig.topper, olista01, rengolin, stoklund Reviewed By: olista01 Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D40011 llvm-svn: 318759
* [X86][XOP] Add missing scheduler classes to XOP instructionsSimon Pilgrim2017-11-211-28/+39
| | | | | | All match equivalent basic classes (WritePHAdd, WriteFAdd etc.) according to both the AMD 15h SOG and Agner's tables. llvm-svn: 318758
* [RISCV][NFC] Clean up RISCVDAGToDAGISel::SelectAlex Bradbury2017-11-211-14/+9
| | | | | | | | | | As pointed out in post-commit review of r318738, `return ReplaceNode(..)` when both ReplaceNode and the current function return void is confusing. This patch moves to using a more obvious early return, and moves to just using an if to catch the one case we currently care about. A future patch that adds further custom instruction selection can introduce a switch. llvm-svn: 318757
* [ARM] Use SEH exceptions on thumbv7-windowsMartell Malone2017-11-211-1/+1
| | | | | | | | Reviewers: mstorsjo Differential Revision: https://reviews.llvm.org/D40286 llvm-svn: 318756
* [X86][LWP] Add missing LWP itinerary class to lwpins instructionsSimon Pilgrim2017-11-211-2/+2
| | | | | | It's on all other LWP instruction but I missed it from lwpins, despite similar scheduling behaviour. llvm-svn: 318751
* [MI scheduler] Fix VADD and VSUB in cortex-a57 modelEugene Leviant2017-11-213-2/+54
| | | | | | | | This patch fixes instregex for interger vector add/sub instructions Differential revision: https://reviews.llvm.org/D40254 llvm-svn: 318749
* [x86][icelake]BITALGCoby Tayree2017-11-2115-0/+544
| | | | | | | vpopcnt{b,w} Differential Revision: https://reviews.llvm.org/D40213 llvm-svn: 318748
* [ARM GlobalISel] Add comment for r318398. NFC.Diana Picus2017-11-211-0/+5
| | | | | | | Mention the purpose of the BICri tests added by r318398, as requested in post-commit review. llvm-svn: 318747
* [x86][icelake]VNNICoby Tayree2017-11-2115-0/+1845
| | | | | | | | | Introducing Vector Neural Network Instructions, consisting of: vpdpbusd{s} vpdpwssd{s} Differential Revision: https://reviews.llvm.org/D40208 llvm-svn: 318746
* [x86][icelake]vbmi2Coby Tayree2017-11-2115-10/+6956
| | | | | | | | | | | introducing vbmi2, consisting of vpcompress{b,w} vpexpand{b,w} vpsh{l,r}d{w,d,q} vpsh{l,r}dv{w,d,q} Differential Revision: https://reviews.llvm.org/D40206 llvm-svn: 318745
* SLPVectorizer.cpp: Avoid std::stable_sort(properlyDominates()).NAKAMURA Takumi2017-11-212-23/+162
| | | | | | | properlyDominates() shouldn't be used as sort key. It causes different output between stdlibc++ and libc++. Instead, I introduced RPOT. In most cases, it works for CSE. llvm-svn: 318743
* [x86][icelake]vpclmulqdq introductionCoby Tayree2017-11-2118-64/+446
| | | | | | | an icelake promotion of pclmulqdq Differential Revision: https://reviews.llvm.org/D40101 llvm-svn: 318741
* [x86][icelake]VAES introductionCoby Tayree2017-11-2114-26/+700
| | | | | | | an icelake promotion of AES Differential Revision: https://reviews.llvm.org/D40078 llvm-svn: 318740
* [RISCV] Use register X0 (ZERO) for constant 0Alex Bradbury2017-11-214-29/+43
| | | | | | | | | | | | The obvious approach of defining a pattern like the one below actually doesn't work: `def : Pat<(i32 0), (i32 X0)>;` As was noted when Lanai made this change (https://reviews.llvm.org/rL288215), attempting to handle the constant 0 in tablegen leads to assertions due to a physical register being used where a virtual register is expected. llvm-svn: 318738
* [RISCV] Support and tests for a variety of additional LLVM IR constructsAlex Bradbury2017-11-2117-15/+1566
| | | | | | | | | | | | | | | | | | | | | | Previous patches primarily ensured that codegen was possible for the standard RISC-V instructions. However, there are a number of IR inputs that wouldn't be appropriately lowered. This patch both adds test cases and supports lowering for a number of these cases: * Improved sext/zext/trunc support * Support for setcc variants that don't map directly to RISC-V instructions * Lowering mul, and hence support for external symbols * addc, adde, subc, sube * mulhs, srem, mulhu, urem, udiv, sdiv * {srl,sra,shl}_parts * brind * br_jt * bswap, ctlz, cttz, ctpop * rotl, rotr * BlockAddress operands Differential Revision: https://reviews.llvm.org/D29938 llvm-svn: 318737
* [RISCV] Implement lowering of ISD::SELECTAlex Bradbury2017-11-215-1/+292
| | | | | | | | | | | | | | Although ISD::SELECT_CC is a more natural match for RISCVISD::SELECT_CC (and ultimately the integer RISC-V conditional branch instructions), we choose to expand ISD::SELECT_CC and lower ISD::SELECT. The appropriate compare+branch will be created in the case where an ISD::SELECT condition value is created by an ISD::SETCC node, which operates on XLen types. Other datatypes such as floating point don't have conditional branch instructions, and lowering ISD::SELECT allows more flexibility for handling these cases. Differential Revision: https://reviews.llvm.org/D29937 llvm-svn: 318735
* [XRay] Use optimistic logging model for FDR modeDean Michael Berris2017-11-211-22/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Before this change, the FDR mode implementation relied on at thread-exit handling to return buffers back to the (global) buffer queue. This introduces issues with the initialisation of the thread_local objects which, even through the use of pthread_setspecific(...) may eventually call into an allocation function. Similar to previous changes in this line, we're finding that there is a huge potential for deadlocks when initialising these thread-locals when the memory allocation implementation is also xray-instrumented. In this change, we limit the call to pthread_setspecific(...) to provide a non-null value to associate to the key created with pthread_key_create(...). While this doesn't completely eliminate the potential for the deadlock(s), it does allow us to still clean up at thread exit when we need to. The change is that we don't need to do more work when starting and ending a thread's lifetime. We also have a test to make sure that we actually can safely recycle the buffers in case we end up re-using the buffer(s) available from the queue on multiple thread entry/exits. This change cuts across both LLVM and compiler-rt to allow us to update both the XRay runtime implementation as well as the library support for loading these new versions of the FDR mode logging. Version 2 of the FDR logging implementation makes the following changes: * Introduction of a new 'BufferExtents' metadata record that's outside of the buffer's contents but are written before the actual buffer. This data is associated to the Buffer handed out by the BufferQueue rather than a record that occupies bytes in the actual buffer. * Removal of the "end of buffer" records. This is in-line with the changes we described above, to allow for optimistic logging without explicit record writing at thread exit. The optimistic logging model operates under the following assumptions: * Threads writing to the buffers will potentially race with the thread attempting to flush the log. To avoid this situation from occuring, we make sure that when we've finalized the logging implementation, that threads will see this finalization state on the next write, and either choose to not write records the thread would have written or write the record(s) in two phases -- first write the record(s), then update the extents metadata. * We change the buffer queue implementation so that once it's handed out a buffer to a thread, that we assume that buffer is marked "used" to be able to capture partial writes. None of this will be safe to handle if threads are racing to write the extents records and the reader thread is attempting to flush the log. The optimism comes from the finalization routine being required to complete before we attempt to flush the log. This is a fairly significant semantics change for the FDR implementation. This is why we've decided to update the version number for FDR mode logs. The tools, however, still need to be able to support older versions of the log until we finally deprecate those earlier versions. Reviewers: dblaikie, pelikan, kpw Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39526 llvm-svn: 318733
* [X86] Simplify type constraints for AVX2 masked gather.Craig Topper2017-11-211-19/+14
| | | | | | We don't need separate 32 and 64 node types. We can use SDTCisInt and SDTCisSameSizeAs to ensure the mask size the result type and is integer. llvm-svn: 318732
* Revert "[CGP] Enable complex addr mode (2nd attempt)"Serguei Katkov2017-11-211-1/+1
| | | | | | Revert the patch rl318728 causing buildbot hangs-ups. llvm-svn: 318731
* [X86] Simplify the predicates for avx2 masked gather patterns.Craig Topper2017-11-211-33/+17
| | | | | | We don't need a dyn_cast and we only need to check the type of the index. The base ptr is guaranteed to be scalar. llvm-svn: 318730
* move static function. NFCRafael Espindola2017-11-211-26/+24
| | | | llvm-svn: 318729
* [CGP] Enable complex addr mode (2nd attempt)Serguei Katkov2017-11-211-1/+1
| | | | | | | 2nd attempt to enable complex addr modes after fix of the crash by rL318638. llvm-svn: 318728
* [AMDGPU] Fix DAGTypeLegalizer::SplitInteger for shift amount typeYaxun Liu2017-11-213-8/+17
| | | | | | | | | | | | | | | DAGTypeLegalizer::SplitInteger uses default pointer size as shift amount constant type, which causes less performant ISA in amdgcn---amdgiz target since the default pointer type is i64 whereas the desired shift amount type is i32. This patch fixes that by using TLI.getScalarShiftAmountTy in DAGTypeLegalizer::SplitInteger. The X86 change is necessary since splitting i512 requires shifting amount of 256, which cannot be held by i8. Differential Revision: https://reviews.llvm.org/D40148 llvm-svn: 318727
* Split a rename_handle out of rename on windows.Rafael Espindola2017-11-211-3/+13
| | | | llvm-svn: 318725
* Add default values for member functions.Richard Trieu2017-11-211-0/+2
| | | | | | | | Initialize IsVis2 and IsVis3 in SparcSubtarget::initializeSubtargetDependencies. MSan detected uninitialized read of IsVis3 after r318704. Initializing the variables to false will prevent undefined behavior. llvm-svn: 318724
* Re-revert "Refactor debuginfo-tests."Zachary Turner2017-11-214-20/+11
| | | | | | | | | | This is still breaking greendragon. At this point I give up until someone can fix the greendragon bots, and I will probably abandon this effort in favor of using a private github repository. llvm-svn: 318722
* xray-record-yaml.h: Remove unused fileDavid Blaikie2017-11-211-102/+0
| | | | llvm-svn: 318715
* llvm-rc/ResourceScriptTokenList.h: Turns this into a .def file to imply that ↵David Blaikie2017-11-215-16/+9
| | | | | | | | it's non-modular Also undef the macros at the end of the file to make it easier to use. llvm-svn: 318714
* XRayRecord.h: Add missing #includeDavid Blaikie2017-11-211-0/+1
| | | | llvm-svn: 318713
* YAML/XRay/std::vector: Fix ODR violation by removing local specializationDavid Blaikie2017-11-211-10/+0
| | | | | | | | There's a generic partial specialization for all std::vector<T> that does what's desired, so no need for this full specialization that's causing an ODR violation anyway. llvm-svn: 318712
* [SCCP] If we replace with a constant, we can't replace with a range.Davide Italiano2017-11-211-1/+3
| | | | | | This microoptimization is NFC. llvm-svn: 318711
* Revert r318678 to fix Clang testRichard Trieu2017-11-219-32/+36
| | | | | | r318678 caused the Clang test CodeGen/ms-inline-asm.c to start failing. llvm-svn: 318710
* [msan] Don't sanitize "nosanitize" instructionsVitaly Buka2017-11-203-18/+62
| | | | | | | | | | Reviewers: eugenis Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40205 llvm-svn: 318708
* [SelectionDAG] When promoting the result of a VSELECT, make sure we promote ↵Craig Topper2017-11-202-3/+16
| | | | | | | | | | | | the condition to the SetCC type for the final result type not the original type. Normally this would be cleaned up by promoting the condition operand next. But in the attached case we promoted the result from v2i48 to v2i64 and the condition from v2i1 to v2i48. Then we tried to "promote" the v2i48 condition back to v2i1 because that's what the SetCC result type for v2i64 is on X86 with VLX. But promote is either a NOP or SIGN_EXTEND and this would need a truncation. With the change here we now get the SetCC type of v2i1 when we're handling the result promotion and the operand no longer needs to be promoted itself. Fixes PR35272. llvm-svn: 318706
* [Sparc] efficient pattern for UINT_TO_FP conversionFedor Sergeev2017-11-204-30/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: while investigating performance degradation of imagick benchmark there were found inefficient pattern for UINT_TO_FP conversion. That pattern causes RAW hazard in assembly code. Specifically, uitofp IR operator results in poor assembler : st %i0, [%fp - 952] ldd [%fp - 952], %f0 it stores 32-bit integer register into memory location and then loads 64-bit floating point data from that location. That is exactly RAW hazard case. To optimize that case it is possible to use SPISD::ITOF and SPISD::XTOF for conversion from integer to floating point data type and to use ISD::BITCAST to copy from integer register into floating point register. The fix is to write custom UINT_TO_FP pattern using SPISD::ITOF, SPISD::XTOF, ISD::BITCAST. Patch by Alexey Lapshin Reviewers: fedor.sergeev, jyknight, dcederman, lero_chris Reviewed By: jyknight Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36875 llvm-svn: 318704
* Add ADL support to range based <algorithm> extensionsDavid Blaikie2017-11-202-41/+124
| | | | | | | | | | | | | | | | | This adds support for ADL in the range based <algorithm> extensions (llvm::for_each etc.). Also adds the helper functions llvm::adl::begin and llvm::adl::end which wrap std::begin and std::end with ADL support. Saw this was missing from a recent llvm weekly post about adding llvm::for_each and thought I might add it. Patch by Stephen Dollberg! Differential Revision: https://reviews.llvm.org/D40006 llvm-svn: 318703
* Resubmit "Refactor debuginfo-tests" again.Zachary Turner2017-11-204-11/+20
| | | | | | | | | | | | This was reverted due to the tests being run twice on some build bots. Each run had a slightly different configuration due to the way in which it was being invoked. This fixes the problem (albeit in a somewhat hacky way). Hopefully in the future we can get rid of the workflow of running debuginfo-tests as part of clang, and then this hack can go away. llvm-svn: 318697
* Fix a lld-x86_64-darwin13 build error.Hiroshi Yamauchi2017-11-201-2/+1
| | | | | | | | | | | | | | | | | | | Summary: Fix this build error http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/15112/steps/build_Lld/logs/stdio after https://reviews.llvm.org/rL318693 Reviewers: davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40266 llvm-svn: 318696
* bpf: add a test case for trunc-op optimizationYonghong Song2017-11-201-0/+106
| | | | | | | | | | | | | | | | Commit b5cbc7760ab8 ("[bpf] allow direct and indirect calls") allowed more than one function in the bpf program, and commit 114353884415 ("bpf: fix a bug in trunc-op optimization") fixed a bug in trunc-op optimization which only showed up with more than one function in the bpf program. This patch added a test case for trunc-op optimization for bpf programs with two functions. Reverting commit "bpf: fix a bug in trunc-op optimization" will cause failure for this test case. Signed-off-by: Yonghong Song <yhs@fb.com> llvm-svn: 318695
* Add heuristics for irreducible loop metadata under PGOHiroshi Yamauchi2017-11-204-12/+112
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add the following heuristics for irreducible loop metadata: - When an irreducible loop header is missing the loop header weight metadata, give it the minimum weight seen among other headers. - Annotate indirectbr targets with the loop header weight metadata (as they are likely to become irreducible loop headers after indirectbr tail duplication.) These greatly improve the accuracy of the block frequency info of the Python interpreter loop (eg. from ~3-16x off down to ~40-55% off) and the Python performance (eg. unpack_sequence from ~50% slower to ~8% faster than GCC) due to better register allocation under PGO. Reviewers: davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39980 llvm-svn: 318693
* Fix spelling in comment. NFCI.Simon Pilgrim2017-11-201-1/+1
| | | | llvm-svn: 318687
* Revert "[SelectionDAG] Make sorting predicate stronger to remove ↵Mandeep Singh Grang2017-11-201-9/+4
| | | | | | | | | | non-deterministic ordering" This broke the bots. Reverting this until I can fix the failures. This reverts commit 5a3db2856d12a3c4b400f487d39f8f05989e79f0. llvm-svn: 318686
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-11-201-2/+4
| | | | | | Fix the modeling of test and branch. llvm-svn: 318685
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