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* [Hexagon] Adding DoubleRegs decoder. Moving C2_mux and A2_nop. Adding ↵Colin LeMahieu2014-12-054-10/+62
| | | | | | combine imm-imm form. llvm-svn: 223494
* Fix a bug when pretty-printing DW_OP_deref.Adrian Prantl2014-12-053-1/+7
| | | | llvm-svn: 223493
* Regenerate this stale testcase from source.Adrian Prantl2014-12-051-114/+112
| | | | llvm-svn: 223492
* [CodeGenPrepare] Use variables for reused values. NFC.Ahmed Bougacha2014-12-051-4/+6
| | | | llvm-svn: 223491
* [Hexagon] [NFC] Rearranging patterns and mux instruction.Colin LeMahieu2014-12-051-38/+38
| | | | llvm-svn: 223488
* [Hexagon] [NFC] Rearranging def order.Colin LeMahieu2014-12-051-28/+27
| | | | llvm-svn: 223487
* Refactor duplicated code. NFC.Rafael Espindola2014-12-051-26/+16
| | | | llvm-svn: 223486
* [Hexagon] Adding combine reg-reg forms.Colin LeMahieu2014-12-052-1/+22
| | | | llvm-svn: 223485
* [Hexagon] Marking several instructions as isCodeGenOnly=0 and adding direct ↵Colin LeMahieu2014-12-054-4/+42
| | | | | | disassembly tests for many instructions. llvm-svn: 223482
* Be less conservative about when we build the gold plugin.Rafael Espindola2014-12-052-16/+2
| | | | | | | It is only build if LLVM_BINUTILS_INCDIR is explicitly given, so there is no point in having extra restrictions. llvm-svn: 223481
* LLVMContext: Store APInt/APFloat directly into the ConstantInt/FP DenseMaps.Benjamin Kramer2014-12-053-57/+26
| | | | | | | | Required some APInt massaging to get proper empty/tombstone values. Apart from making the code a bit simpler this also reduces the bucket size of the ConstantInt map from 32 to 24 bytes. llvm-svn: 223478
* Improvements to ARM assembler testsAsiri Rathnayake2014-12-051-70/+445
| | | | | | | | | | | | | | | | | | | | | | | | No functional changes. Got myself bitten in r223113 when adding support for modified immediate syntax (regressions reported by joerg@britannica.bec.de, fixes in r223366 and r223381). Our assembler tests did not cover serveral different syntax variants. This patch expands the test coverage to check for the following cases: 1. Modified immediate operands may be expressed with expressions, as in #(4 * 2) instead of #8. 2. Modified immediate operands may be _optionally_ prefixed by a '#' symbol or a '$' symbol. 3. Certain instructions (e.g. ADD) support single input register variants; [ADD r0, #mod_imm] is same as [ADD r0, r0, #mod_imm]. 4. Certain instructions have aliases which convert plain immediates to modified immediates. For an example, [ADD r0, -10] is not valid because -10 (in two's complement) cannot be encoded as a modified immediate, but ARMInstrInfo.td defines an alias which can transform this into a [SUB r0, 10]. llvm-svn: 223475
* Small cleanup on how we clear constant variables. NFC.Rafael Espindola2014-12-051-14/+9
| | | | llvm-svn: 223474
* Update TargetTriple format info.Chad Rosier2014-12-051-0/+1
| | | | | | Phabricator revision: http://reviews.llvm.org/D6543 llvm-svn: 223473
* Fix typos in llvm/IR/Module.hChad Rosier2014-12-051-2/+2
| | | | | | Phabricator revision: http://reviews.llvm.org/D6535 llvm-svn: 223472
* Use an early return. NFC.Rafael Espindola2014-12-051-19/+19
| | | | llvm-svn: 223470
* [msan] Avoid extra origin address realignment.Evgeniy Stepanov2014-12-052-21/+97
| | | | | | | | | Do not realign origin address if the corresponding application address is at least 4-byte-aligned. Saves 2.5% code size in track-origins mode. llvm-svn: 223464
* [X86] Avoid introducing extra shuffles when lowering packed vector shifts.Andrea Di Biagio2014-12-053-16/+173
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When lowering a vector shift node, the backend checks if the shift count is a shuffle with a splat mask. If so, then it introduces an extra dag node to extract the splat value from the shuffle. The splat value is then used to generate a shift count of a target specific shift. However, if we know that the shift count is a splat shuffle, we can use the splat index 'I' to extract the I-th element from the first shuffle operand. The advantage is that the splat shuffle may become dead since we no longer use it. Example: ;; define <4 x i32> @example(<4 x i32> %a, <4 x i32> %b) { %c = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer %shl = shl <4 x i32> %a, %c ret <4 x i32> %shl } ;; Before this patch, llc generated the following code (-mattr=+avx): vpshufd $0, %xmm1, %xmm1 # xmm1 = xmm1[0,0,0,0] vpxor %xmm2, %xmm2 vpblendw $3, %xmm1, %xmm2, %xmm1 # xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7] vpslld %xmm1, %xmm0, %xmm0 retq With this patch, the redundant splat operation is removed from the code. vpxor %xmm2, %xmm2 vpblendw $3, %xmm1, %xmm2, %xmm1 # xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7] vpslld %xmm1, %xmm0, %xmm0 retq llvm-svn: 223461
* Add missing FP build attribute tests.Charlie Turner2014-12-052-28/+150
| | | | | | | | | | | | | | | | | | | | | The test file test/CodeGen/ARM/build-attributes.ll was missing several floating-point build attribute tests. The intention of this commit is that for each CPU / architecture currently tested, there are now tests that make sure the following attributes are sufficiently checked, * Tag_ABI_FP_rounding * Tag_ABI_FP_denormal * Tag_ABI_FP_exceptions * Tag_ABI_FP_user_exceptions * Tag_ABI_FP_number_model Also in this commit, the -unsafe-fp-math flag has been augmented with the full suite of flags Clang sends to LLVM when you pass -ffast-math to Clang. That is, `-unsafe-fp-math' has been changed to `-enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast' Change-Id: I35d766076bcbbf09021021c0a534bf8bf9a32dfc llvm-svn: 223454
* Revert "r223440 - Consider subregs when calling MI::registerDefIsDead for ↵Hal Finkel2014-12-052-175/+1
| | | | | | | | | phys deps" Reverting this because, while it fixes the problem in the reduced test case, it does not fix the problem in the full test case from the bug report. llvm-svn: 223442
* Consider subregs when calling MI::registerDefIsDead for phys depsHal Finkel2014-12-052-1/+175
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The scheduling dependency graph is built bottom-up within each scheduling region, and ScheduleDAGInstrs::addPhysRegDeps is called to add output/anti dependencies, based on physical registers, to the SUs for instructions based on those that come before them. In the test case, we start before post-RA scheduling with a block that looks like this: ... INLINEASM <... andc $0,$0,$2 stdcx. $0,0,$3 bne- 1b > [sideeffect] [mayload] [maystore] [attdialect], $0:[regdef-ec:G8RC], %X6<earlyclobber,def,dead>, $1:[mem], %X3<kill>, $2:[reguse:G8RC], %X5<kill>, $3:[reguse:G8RC], %X3, $4:[mem], %X3, $5:[clobber], %CC<earlyclobber,imp-def,dead>, <<badref>> ... %X4<def,dead> = ANDIo8 %X4<kill>, 1, %CR0<imp-def,dead>, %CR0GT<imp-def> ... %R29<def> = ISEL %R3<undef>, %R4<kill>, %CR0GT<kill> where it is relevant that %CC is an alias to %CR0, and that %CR0GT is a subregister of %CR0. However, for post-RA scheduling, no dependency was added to prevent the INLINEASM from being scheduled in between the ANDIo8 and the ISEL (which communicate via the %CR0GT register). In ScheduleDAGInstrs::addPhysRegDeps, when called for the %CC operand, we'd iterate over all of its aliases (which include %CC itself and also %CR0), and look for previously-encountered defs of those registers. We'd find the ANDIo8, but decide not to add a dependency between the INLINEASM and the ANDIo8 because both the INLINEASM's def of %CC is dead, and also the ANDIo8 def of %CR0 is dead. This ignores, however, that ANDIo8 has a non-dead def of %CR0GT, a subregister of %CR0, and thus a dependency still must exist. To fix this problem, when calling registerDefIsDead on the SU with the def, we also check all subregisters for possible non-dead defs, and add the dependency if any are found. Fixes PR21742. llvm-svn: 223440
* ADT: Remove GetStringMapEntryFromValue()Duncan P. N. Exon Smith2014-12-051-13/+0
| | | | | | | It relies on undefined behaviour, since `StringMapEntry<>` is not a standard layout type. There are no users anyway. llvm-svn: 223439
* IR: Stop relying on GetStringMapEntryFromValue()Duncan P. N. Exon Smith2014-12-052-2/+5
| | | | | | It relies on undefined behaviour. llvm-svn: 223438
* Cleanup: Calls to getDwarfRegNum() may actually fail, if there isAdrian Prantl2014-12-053-27/+44
| | | | | | | | | | | | | no DWARF register number mapping, or if the register was a virtual register that was never materialized. Previously, we would just emit a bogus location, after this patch we don't emit a location at all by doing an early exit. After my bugfix in r223401 today, this doesn't actually happen on any target that I tested this with, but it's still preferable to make the possibility of a failure explicit. llvm-svn: 223428
* Add a comment.Adrian Prantl2014-12-051-1/+1
| | | | llvm-svn: 223427
* Make GetSVN.cmake do its VCS queries with native CMake code.Paul Robinson2014-12-051-5/+70
| | | | | | | | | | This lets the queries work on Windows as well as Linux. This does mean make and cmake aren't using the same scripts to do the queries (again), but at least GetSVN.cmake understands git and git-svn as well as svn now. llvm-svn: 223425
* linkGlobalVariableProto never returns null. Simplify the caller. NFC.Rafael Espindola2014-12-051-6/+3
| | | | llvm-svn: 223424
* Rename the x86 isTargetMacho to isTargetMachO for uniformity.Eric Christopher2014-12-054-8/+8
| | | | llvm-svn: 223421
* Both of these subtargets have functions that check whether orEric Christopher2014-12-052-3/+2
| | | | | | not the target is mach-o. Use them. llvm-svn: 223420
* Move merging of alignment to a central location. NFC.Rafael Espindola2014-12-051-19/+3
| | | | llvm-svn: 223418
* Add a few extra cases to the test. NFC.Rafael Espindola2014-12-052-5/+30
| | | | llvm-svn: 223417
* Re-add support to llvm-objdump for Mach-O universal files and archives with ↵Kevin Enderby2014-12-046-19/+267
| | | | | | | | | | | -macho with fixes. Includes the move of tests for llvm-objdump for universal files to an X86 directory. And the fix where it was failing on linux Rafael tracked down with asan. I had both Jim Grosbach and Adam Hemet look over the second fix since I could not set up asan to reproduce with the old version but not with the fix. llvm-svn: 223416
* [X86] Delete dead code in fcopysign lowering. NFC.Ahmed Bougacha2014-12-041-11/+0
| | | | | | | | | r32900 introduced custom lowering for fcopysign, with two checks to change the magnitude value's type if it's larger/smaller than the sign value's type. r32932 replaced that code for the smaller case. r43205 did the same for the larger case, but left the old code, now dead. llvm-svn: 223415
* Convert test to use an extra Input file. NFC.Rafael Espindola2014-12-043-8/+9
| | | | llvm-svn: 223414
* Revert "Fix UBSan report in StringMap implementation."Alexey Samsonov2014-12-041-1/+4
| | | | | | | This reverts commit r223402. Some bots fail with -Winvalid-offsetof warning. llvm-svn: 223407
* Simplify implementation and testcase of r223401 based on feedback from dblaikie.Adrian Prantl2014-12-042-27/+20
| | | | llvm-svn: 223405
* Fix UBSan report in StringMap implementation.Alexey Samsonov2014-12-041-4/+1
| | | | | | Use offsetof() instead of a member access within null pointer. llvm-svn: 223402
* Debug info: If the RegisterCoalescer::reMaterializeTrivialDef() isAdrian Prantl2014-12-042-1/+83
| | | | | | | eliminating all uses of a vreg, update any DBG_VALUE describing that vreg to point to the rematerialized register instead. llvm-svn: 223401
* Add some tests for SimplifyCFG's TurnSwitchRangeIntoICmp(). NFC.Hans Wennborg2014-12-041-0/+50
| | | | llvm-svn: 223396
* Add some tests for SimplifyCFG's ConstantFoldTerminator(). NFC.Hans Wennborg2014-12-041-0/+64
| | | | llvm-svn: 223395
* Also use --icf=safe if we are being linked by gold.Rafael Espindola2014-12-041-1/+1
| | | | llvm-svn: 223394
* Add a FIXME as requested by Renato Golin.Roman Divacky2014-12-041-0/+3
| | | | llvm-svn: 223390
* Silence warning: variable 'buffer' set but not used.Yaron Keren2014-12-041-3/+5
| | | | llvm-svn: 223389
* [x86] Fix isOffsetSuitableForCodeModel kernel code model offsetBruno Cardoso Lopes2014-12-041-1/+1
| | | | | | | Offset == 0 is a valid offset for kernel code model according to the x86_64 System V ABI. Found by inspection, no testcase. llvm-svn: 223383
* [AArch64] Combining Load and IntToFp should check for neon availabilityWeiming Zhao2014-12-042-3/+20
| | | | llvm-svn: 223382
* Fix yet another unseen regression caused by r223113Asiri Rathnayake2014-12-043-15/+33
| | | | | | | | | | r223113 added support for ARM modified immediate assembly syntax. Which assumes all immediate operands are prefixed with a '#'. This assumption is wrong as per the ARMARM - which recommends that all '#' characters be treated optional. The current patch fixes this regression and adds a test case. A follow-up patch will expand the test coverage to other instructions. llvm-svn: 223381
* Fix thumbv4t indirect callsJonathan Roelofs2014-12-044-13/+96
| | | | | | | | | | | | | | | | | | | | | So there are a couple of issues with indirect calls on thumbv4t. First, the most 'obvious' instruction, 'blx' isn't available until v5t. And secondly, the next-most-obvious sequence: 'mov lr, pc; bx rN' doesn't DTRT in thumb code because the saved off pc has its thumb bit cleared, so when the callee returns we end up in ARM mode.... yuck. The solution is to 'bl' to a nearby landing pad with a 'bx rN' in it. We could cut down on code size by sharing the landing pads between call sites that are close enough, but for the moment let's do correctness first and look at performance later. Patch by: Iain Sandoe http://reviews.llvm.org/D6519 llvm-svn: 223380
* Add a test case for argument type coercion in an invoke of a vararg functionPhilip Reames2014-12-041-0/+20
| | | | | | This would have caught the bug I fixed in 223370. llvm-svn: 223378
* Add a section to Statepoint docs mentioning shared bugzilla search and ↵Philip Reames2014-12-041-0/+4
| | | | | | standard mailing lists llvm-svn: 223374
* Detect if the linker is gold and if so always use --gc-sections.Rafael Espindola2014-12-041-1/+15
| | | | llvm-svn: 223372
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