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* Remember to update LiveDebugVariables after per-block splitting.Jakob Stoklund Olesen2011-08-051-1/+5
| | | | llvm-svn: 136996
* Extract per-block splitting into its own method.Jakob Stoklund Olesen2011-08-051-23/+36
| | | | | | No functional change. llvm-svn: 136994
* Delete getMultiUseBlocks and splitSingleBlocks.Jakob Stoklund Olesen2011-08-052-38/+0
| | | | | | | These functions are no longer used, and they are easily replaced with a loop calling shouldSplitSingleBlock and splitSingleBlock. llvm-svn: 136993
* Also use shouldSplitSingleBlock() in the fallback splitting mode.Jakob Stoklund Olesen2011-08-051-8/+18
| | | | | | | Drop the use of SplitAnalysis::getMultiUseBlocks, there is no need to go through a SmallPtrSet any more. llvm-svn: 136992
* Split around single instructions to enable register class inflation.Jakob Stoklund Olesen2011-08-053-1/+35
| | | | | | | | | | | | | Normally, we don't create a live range for a single instruction in a basic block, the spiller does that anyway. However, when splitting a live range that belongs to a proper register sub-class, inserting these extra COPY instructions completely remove the constraints from the remainder interval, and it may be allocated from the larger super-class. The spiller will mop up these small live ranges if we end up spilling anyway. It calls them snippets. llvm-svn: 136989
* ARM load instruction shifted register index operands.Jim Grosbach2011-08-052-7/+16
| | | | | | Parsing and encoding for shifted index operands for load instructions. llvm-svn: 136986
* ARM indexed load assembly parsing and encoding.Jim Grosbach2011-08-053-13/+67
| | | | | | | More parsing support for indexed loads. Fix pre-indexed with writeback parsing for register offsets and handle basic post-indexed offsets. llvm-svn: 136982
* Detect proper register sub-classes.Jakob Stoklund Olesen2011-08-052-2/+18
| | | | | | | | | | | | | | | | | Some instructions require restricted register classes, but most of the time that doesn't affect register allocation. For example, some instructions don't work with the stack pointer, but that is a reserved register anyway. Sometimes it matters, GR32_ABCD only has 4 allocatable registers. For such a proper sub-class, the register allocator should try to enable register class inflation since that makes more registers available for allocation. Make sure only legal super-classes are considered. For example, tGPR is not a proper sub-class in Thumb mode, but in ARM mode it is. llvm-svn: 136981
* ARM refactor indexed store instructions.Jim Grosbach2011-08-055-75/+150
| | | | | | | | | | Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
* Add ARM LDR parsing tests.Jim Grosbach2011-08-051-0/+26
| | | | llvm-svn: 136977
* Fix liveness computations in BranchFolding.Jakob Stoklund Olesen2011-08-051-13/+16
| | | | | | | | | | | | | | | | | | | | | | | The old code would look at kills and defs in one pass over the instruction operands, causing problems with this code: %R0<def>, %CPSR<def,dead> = tLSLri %R5<kill>, 2, pred:14, pred:%noreg %R0<def>, %CPSR<def,dead> = tADDrr %R4<kill>, %R0<kill>, pred:14, %pred:%noreg The last instruction kills and redefines %R0, so it is still live after the instruction. This caused a register scavenger crash when compiling 483.xalancbmk for armv6. I am not including a test case because it requires too much bad luck to expose this old bug. First you need to convince the register allocator to use %R0 twice on the tADDrr instruction, then you have to convince BranchFolding to do something that causes it to run the register scavenger on he bad block. <rdar://problem/9898200> llvm-svn: 136973
* ARM simplify the postidx_reg operand encoding.Jim Grosbach2011-08-054-11/+14
| | | | | | | The immediate portion of the operand is just a boolean (the 'U' bit indicating add vs. subtract). Treat it as such. llvm-svn: 136969
* ARM use a dedicated printer for postidx_reg operands.Jim Grosbach2011-08-053-1/+11
| | | | llvm-svn: 136968
* Add missing register constraint for some VLD3/VLD4 pseudo instructions.Bob Wilson2011-08-051-1/+2
| | | | | | <rdar://problem/9878189> llvm-svn: 136962
* Silence unused variable warnings in release builds.Chandler Carruth2011-08-051-0/+2
| | | | llvm-svn: 136956
* Fix http://llvm.org/bugs/show_bug.cgi?id=10583\n - test for 1 and 2 byte ↵Jason W Kim2011-08-051-15/+11
| | | | | | fixups to be added llvm-svn: 136954
* Temporarily revert r135528 which distinguishes between two copies of oneChandler Carruth2011-08-054-28/+3
| | | | | | | | | | | | | | | | | | | inlined variable, based on the discussion in PR10542. This explodes the runtime of several passes down the pipeline due to a large number of "copies" remaining live across a large function. This only shows up with both debug and opt, but when it does it creates a many-minute compile when self-hosting LLVM+Clang. There are several other cases that show these types of regressions. All of this is tracked in PR10542, and progress is being made on fixing the issue. Once its addressed, the re-instated, but until then this restores the performance for self-hosting and other opt+debug builds. Devang, let me know if this causes any trouble, or impedes fixing it in any way, and thanks for working on this! llvm-svn: 136953
* Fix broken encodings for the Thumb2 LDRD/STRD instructions.Owen Anderson2011-08-043-13/+42
| | | | llvm-svn: 136942
* ARM assembly parsing and encoding for LDR instructions.Jim Grosbach2011-08-042-8/+37
| | | | | | | Enhance support for LDR instruction assembly parsing for post-indexed addressing with immediate values. Add tests. llvm-svn: 136940
* Count the total amount of stack space used in compiled functions.Jakob Stoklund Olesen2011-08-041-1/+4
| | | | | | Patch by Ivan Krasin! llvm-svn: 136921
* Print DBG_VALUE variable's location info as a comment.Devang Patel2011-08-041-1/+13
| | | | llvm-svn: 136916
* Increment counter inside insertDebugValue().Devang Patel2011-08-041-2/+1
| | | | llvm-svn: 136915
* We need to map DebugLoc. It leads to Fuction * (through subprogram entry ↵Devang Patel2011-08-043-3/+51
| | | | | | node) which should be appropriately mapped. llvm-svn: 136910
* Linke NamedMDNodes after linking global values as comment suggests.Devang Patel2011-08-043-5/+63
| | | | llvm-svn: 136909
* allow \r's in .s files.Chris Lattner2011-08-041-1/+1
| | | | llvm-svn: 136908
* Introduce adjustFixupOffset that adjusts the fixup offset of a relocation.Roman Divacky2011-08-042-12/+16
| | | | | | | | This is meant to be overriden by backends. Implement an override on PowerPC which adjusts the offset by 2 for ha16/lo16 relocation kinds. This removes a commented out hack and enables hello world to be compiled on PowerPC. llvm-svn: 136905
* Add counter.Devang Patel2011-08-041-1/+4
| | | | llvm-svn: 136901
* Fix an obvious type. Patch by Ivan Krasin.Evan Cheng2011-08-041-1/+1
| | | | llvm-svn: 136900
* Fix an obvious type. Patch by Ivan Krasin.Evan Cheng2011-08-041-1/+1
| | | | llvm-svn: 136899
* LDCL_POST and STCL_POST need one's-complement offsets, rather than two's ↵Owen Anderson2011-08-044-1/+24
| | | | | | complement offsets. Add an appropriate immediate type for them. llvm-svn: 136896
* Fix the bitwidth of the remaining fields.Rafael Espindola2011-08-0450-540/+536
| | | | llvm-svn: 136884
* Fix a place that was clearly forgotten when the type legalizationDuncan Sands2011-08-041-2/+2
| | | | | | | logic moved over to its own enum. Noticed by Andrey Karpov with the PVS-studio tool. llvm-svn: 136881
* print st_shndx with the correct number of bits.Rafael Espindola2011-08-0425-82/+82
| | | | llvm-svn: 136880
* Add obviously missing "break". Noticed by Andrey Karpov withDuncan Sands2011-08-041-0/+1
| | | | | | the PVS-studio tool. llvm-svn: 136878
* print st_other with the correct number of bits.Rafael Espindola2011-08-0425-84/+84
| | | | llvm-svn: 136877
* print st_type with the correct number of bits.Rafael Espindola2011-08-0428-95/+95
| | | | llvm-svn: 136875
* Print st_bind with the correct number of bits.Rafael Espindola2011-08-0431-99/+101
| | | | llvm-svn: 136874
* Print r_sym with the correct number of bits.Rafael Espindola2011-08-048-29/+29
| | | | llvm-svn: 136873
* Print r_type with the correct number of bits.Rafael Espindola2011-08-0410-42/+44
| | | | llvm-svn: 136872
* Another counter goes decimal.Rafael Espindola2011-08-0430-95/+95
| | | | llvm-svn: 136871
* Change anther counter to decimal.Rafael Espindola2011-08-0437-167/+167
| | | | llvm-svn: 136870
* Don't print a counter in hex.Rafael Espindola2011-08-0424-38/+38
| | | | llvm-svn: 136869
* Add an assert to check that the Addend fits the file format.Rafael Espindola2011-08-041-0/+6
| | | | llvm-svn: 136868
* Print all the bits in the addend.Rafael Espindola2011-08-0426-129/+123
| | | | llvm-svn: 136867
* Reword.Jay Foad2011-08-041-2/+2
| | | | llvm-svn: 136866
* Fix what seems an obvious typo. Patch by Ivan Krasin. ProblemDuncan Sands2011-08-041-1/+1
| | | | | | reported at http://habrahabr.ru/blogs/compilers/125626/. llvm-svn: 136865
* Reverting r136884 updateUnloop, which crashed a linux builder.Andrew Trick2011-08-043-266/+53
| | | | llvm-svn: 136857
* Fix http://llvm.org/bugs/show_bug.cgi?id=10568Jason W Kim2011-08-043-1/+30
| | | | | | Move the reloc size assert into AsmBackend - where it is more apropos. llvm-svn: 136855
* Only access both operands of an INSERT_SUBVECTOR if it is an INSERT_SUBVECTOR.Bill Wendling2011-08-042-9/+33
| | | | | | Fixes PR10527. llvm-svn: 136853
* ARM refactoring assembly parsing of memory address operands.Jim Grosbach2011-08-0316-638/+577
| | | | | | | | | | | | | | | | | | | | | | Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
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