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* [CMake] Refactor add_llvm_implicit_projects to be reusableChris Bieneman2016-03-081-3/+7
| | | | | | This adds llvm_add_implicit_projects which takes a project name and is wrapped by add_llvm_implicit_projects. llvm-svn: 262948
* [AArch64] Disable the MI scheduler to turn bots green after r262942.Chad Rosier2016-03-081-4/+4
| | | | llvm-svn: 262944
* Revert r262759 and r262760.Quentin Colombet2016-03-082-39/+0
| | | | | | | | The fix consisting in using the library call for atomic compare and swap when the instruction is not safe to use may be incorrect. Indeed the library call may not exist on all platform. In other words, we need a better fix! llvm-svn: 262943
* [AArch64] Add MMOs to unscaled pairs.Chad Rosier2016-03-081-3/+2
| | | | | | | Test to be committed in follow up commit, per discussion in D17097. http://reviews.llvm.org/D17097 llvm-svn: 262942
* rangify, fix function names; NFCISanjay Patel2016-03-081-27/+22
| | | | llvm-svn: 262940
* Invoke DAG postprocessing in the post-RA schedulerKrzysztof Parzyszek2016-03-081-0/+2
| | | | | | | This was inadvertently omitted from r262774, which added the mutation interface. llvm-svn: 262939
* don't repeat function names in documentation comments; NFCSanjay Patel2016-03-081-4/+4
| | | | llvm-svn: 262937
* [ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC)Artyom Skrobov2016-03-083-107/+74
| | | | | | | | | | Reviewers: t.p.northover, grosbach, resistor Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D17636 llvm-svn: 262936
* Revert r262599 "[X86][SSE] Improve vector ZERO_EXTEND by combining to ↵Hans Wennborg2016-03-084-60/+43
| | | | | | | | ZERO_EXTEND_VECTOR_INREG" This caused PR26870. llvm-svn: 262935
* Fix problem with uninitilialized bool found by asan.Manuel Klimek2016-03-081-1/+1
| | | | llvm-svn: 262934
* Add DAG mutation interface to the DFA packetizerKrzysztof Parzyszek2016-03-082-0/+28
| | | | llvm-svn: 262930
* AVX512: Add extract_subvector patterns v8i1->v4i1 , v4i1->v2i1.Igor Breger2016-03-082-0/+31
| | | | | | Differential Revision: http://reviews.llvm.org/D17953 llvm-svn: 262929
* [gold] Avoid assertion failures when taking a pointer to an empty vector.Benjamin Kramer2016-03-081-1/+1
| | | | llvm-svn: 262926
* [llvm-config] Get rid of code related to the Makefile buildsFilipe Cabecinhas2016-03-081-32/+5
| | | | | | | | | | | | Summary: I left --build-system for backwards compat, in case there are scripts using it. Feel free to ask for its removal too. Reviewers: chapuni, tstellarAMD Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D17886 llvm-svn: 262924
* [X86] Regenerated vector float extension testsSimon Pilgrim2016-03-081-19/+65
| | | | llvm-svn: 262919
* Remove pr25342 test-case.Junmo Park2016-03-081-93/+0
| | | | | | This commit removes pr25342 for reverting r262670 clearly. llvm-svn: 262918
* Revert "[InstCombine] Combine A->B->A BitCast"Junmo Park2016-03-082-104/+0
| | | | | | This reverts commit r262670 due to compile failure. llvm-svn: 262916
* SelectionDAG: Appease the bots that don't like my unionJustin Bogner2016-03-081-6/+3
| | | | | | Should fix the breakage in r262902. llvm-svn: 262908
* Fix evaluation order. Spotted by Alexander Riccio!Peter Collingbourne2016-03-081-1/+1
| | | | llvm-svn: 262907
* [Power9] Implement new vsx instructions: load, store instructions for vector ↵Kit Barton2016-03-089-0/+390
| | | | | | | | | | | | | | | | | | | | and scalar We follow the comments mentioned in http://reviews.llvm.org/D16842#344378 to implement this new patch. This patch implements the following vsx instructions: Vector load/store: lxv lxvx lxvb16x lxvl lxvll lxvh8x lxvwsx stxv stxvb16x stxvh8x stxvl stxvll stxvx Scalar load/store: lxsd lxssp lxsibzx lxsihzx stxsd stxssp stxsibx stxsihx 21 instructions Phabricator: http://reviews.llvm.org/D16919 llvm-svn: 262906
* [WebAssembly] Update for spec change from tableswitch to br_table.Dan Gohman2016-03-087-22/+22
| | | | | | | Also note that the operand order changed; the default label is now listed after the regular labels. llvm-svn: 262903
* Re-apply "SelectionDAG: Store SDNode operands in an ArrayRecycler"Justin Bogner2016-03-083-393/+222
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This re-applies r262886 with a fix for 32 bit platforms that have 8 byte pointer alignment, effectively reverting r262892. Original Message: Currently some SDNode operands are malloc'd, some are stored inline in subclasses of SDNode, and some are thrown into a BumpPtrAllocator. This scheme is complex, inconsistent, and makes refactoring SDNodes fairly difficult. Instead, we can allocate all of the operands using an ArrayRecycler that wraps a BumpPtrAllocator. This keeps the cache locality when iterating operands, improves locality when iterating SDNodes without looking at operands, and vastly simplifies the ownership semantics. It also means we stop overallocating SDNodes by 2-3x and will make it simpler to fix the rampant undefined behaviour we have in how we mutate SDNodes from one kind to another (See llvm.org/pr26808). This is NFC other than the changes in memory behaviour, and I ran some LNT tests to make sure this didn't hurt compile time. Not many tests changed: there were a couple of 1-2% regressions reported, but there were more improvements (of up to 4%) than regressions. llvm-svn: 262902
* [MIR] Change the token name for '<' and '>' to be consitent with the LLVM IR ↵Quentin Colombet2016-03-082-4/+4
| | | | | | | | parser. Thanks to Ahmed Bougacha for noticing! llvm-svn: 262899
* [AArch64][GlobalISel] Add a test case for the IRTranslator.Quentin Colombet2016-03-081-0/+18
| | | | llvm-svn: 262898
* [AArch64] Initialize GlobalISel as part of the target initialization.Quentin Colombet2016-03-081-0/+2
| | | | llvm-svn: 262897
* [GlobalISel] Introduce initializer method to support start/stop-after features.Quentin Colombet2016-03-085-25/+37
| | | | llvm-svn: 262896
* [MIR] Teach the parser/printer that generic virtual registers do not need a ↵Quentin Colombet2016-03-083-15/+30
| | | | | | register class. llvm-svn: 262893
* Revert "SelectionDAG: Store SDNode operands in an ArrayRecycler"Justin Bogner2016-03-083-213/+392
| | | | | | | | | Looks like the largest SDNode is different between 32 and 64 bit now, so this is breaking 32 bit bots. Reverting while I figure out a fix. This reverts r262886. llvm-svn: 262892
* A couple more UB fixes for C++14 sized deallocation.Richard Smith2016-03-082-0/+10
| | | | llvm-svn: 262891
* [MIR] Teach the parser how to parse complex types of generic machine ↵Quentin Colombet2016-03-084-14/+62
| | | | | | | | instructions. By complex types, I mean aggregate or vector types. llvm-svn: 262890
* SelectionDAG: Store SDNode operands in an ArrayRecyclerJustin Bogner2016-03-083-392/+213
| | | | | | | | | | | | | | | | | | | | | | | Currently some SDNode operands are malloc'd, some are stored inline in subclasses of SDNode, and some are thrown into a BumpPtrAllocator. This scheme is complex, inconsistent, and makes refactoring SDNodes fairly difficult. Instead, we can allocate all of the operands using an ArrayRecycler that wraps a BumpPtrAllocator. This keeps the cache locality when iterating operands, improves locality when iterating SDNodes without looking at operands, and vastly simplifies the ownership semantics. It also means we stop overallocating SDNodes by 2-3x and will make it simpler to fix the rampant undefined behaviour we have in how we mutate SDNodes from one kind to another (See llvm.org/pr26808). This is NFC other than the changes in memory behaviour, and I ran some LNT tests to make sure this didn't hurt compile time. Not many tests changed: there were a couple of 1-2% regressions reported, but there were more improvements (of up to 4%) than regressions. llvm-svn: 262886
* [MIR] Teach the printer how to print complex types for generic machine ↵Quentin Colombet2016-03-081-1/+2
| | | | | | | | | | | | | instructions. Before this change, we would get the type definition in the middle of the instruction. E.g., %0(48) = G_ADD %struct_alias = type { i32, i16 } %edi, %edi Now, we have just the expected type name: %0(48) = G_ADD %struct_alias %edi, %edi llvm-svn: 262885
* [AsmParser] Expose an API to parse a string starting with a type.Quentin Colombet2016-03-085-5/+180
| | | | | | | | | | | | Without actually parsing a type it is difficult to perdict where the type definition ends. In other words, instead of expecting the user of the parser API to hand over only the relevant bits of the string being parsed, take the whole string, parse the type, and get back the number of characters that have been read. This will be used by the MIR testing infrastructure. llvm-svn: 262884
* Revert revisions 262636, 262643, 262679, and 262682.Easwaran Raman2016-03-0811-446/+53
| | | | llvm-svn: 262883
* [MIR] Print the type of generic machine instructions.Quentin Colombet2016-03-082-1/+5
| | | | llvm-svn: 262880
* [MIR] Teach the mir parser about types on generic machine instructions.Quentin Colombet2016-03-082-1/+35
| | | | llvm-svn: 262879
* [lit] Teach lit about global-isel requirement.Quentin Colombet2016-03-081-0/+14
| | | | llvm-svn: 262878
* [llvm-config] Teach llvm-config about global-isel.Quentin Colombet2016-03-083-0/+5
| | | | | | | | llvm-config can know tell whether or not a build has been configured to support global-isel. Use '--has-global-isel' for that. llvm-svn: 262877
* [tsan] Add support for pointer typed atomic stores, loads, and cmpxchgAnna Zaks2016-03-072-8/+66
| | | | | | | | | | TSan instrumentation functions for atomic stores, loads, and cmpxchg work on integer value types. This patch adds casts before calling TSan instrumentation functions in cases where the value is a pointer. Differential Revision: http://reviews.llvm.org/D17833 llvm-svn: 262876
* [x86] add test to show missing optimizationSanjay Patel2016-03-071-0/+31
| | | | | | | | This should make it clearer how this proposed patch: http://reviews.llvm.org/D11393 ...will change codegen. llvm-svn: 262875
* [x86] simplify test and tighten checksSanjay Patel2016-03-071-15/+22
| | | | | | | | | I noticed this test as part of: http://reviews.llvm.org/D11393 ...which is confusing enough as-is. Let's show the exact codegen, so the changes will be more obvious. llvm-svn: 262874
* [MachineInstr] Get rid of some GlobalISel ifdefs.Quentin Colombet2016-03-072-13/+26
| | | | | | | | Now the type API is always available, but when global-isel is not built the implementation does nothing. Note: The implementation free of ifdefs is WIP and tracked here in PR26576. llvm-svn: 262873
* Remove unused import in Orc C APIAmaury Sechet2016-03-071-1/+0
| | | | | | | | | | | | Summary: It is not used. Reviewers: lhames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D17251 llvm-svn: 262870
* [IR] Provide an API to skip the details of a structured type when printed.Quentin Colombet2016-03-072-2/+12
| | | | | | | The mir infrastructure will need this for generic instructions and currently this feature was only available through the anonymous TypePrinter class. llvm-svn: 262869
* [AsmParser] Add a function to parse a standalone type.Quentin Colombet2016-03-075-0/+155
| | | | | | | This is useful for MIR serialization. Indeed generic machine instructions must have a type and we don't want to duplicate the logic in the MIParser. llvm-svn: 262868
* [MIR] Teach the MIPrinter about size for generic virtual registers.Quentin Colombet2016-03-072-5/+13
| | | | llvm-svn: 262867
* Fix broken example for bitreverse documentationMatt Arsenault2016-03-071-2/+2
| | | | llvm-svn: 262865
* AMDGPU: Match more med3 integer patternsMatt Arsenault2016-03-074-0/+727
| | | | llvm-svn: 262864
* [MIR] Teach the parser how to handle the size of generic virtual registers.Quentin Colombet2016-03-072-8/+53
| | | | llvm-svn: 262862
* [MachineRegisterInfo] Add a method to set the size of a virtual register a ↵Quentin Colombet2016-03-072-0/+9
| | | | | | | | posteriori. This is required for mir testing. llvm-svn: 262861
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