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* Encapsulate PassManager debug flags to avoid static init and cxa_exit.Andrew Trick2013-09-1811-74/+136
| | | | | | | | | | | | | | This puts all the global PassManager debugging flags, like -print-after-all and -time-passes, behind a managed static. This eliminates their static initializers and, more importantly, exit-time destructors. The only behavioral change I anticipate is that tools need to initialize the PassManager before parsing the command line in order to export these options, which makes sense. Tools that already initialize the standard passes (opt/llc) don't need to do anything new. llvm-svn: 190974
* whitespaceAndrew Trick2013-09-186-33/+33
| | | | llvm-svn: 190973
* Fix two issues regarding Got pointer (GP) setup.Reed Kotler2013-09-183-14/+26
| | | | | | | | | | | | | | | 1) make sure that the first two instructions of the sequence cannot separate from each other. The linker requires that they be sequential. If they get separated, it can still work but it will not work in all cases because the first of the instructions mostly involves the hi part of the pc relative offset and that part changes slowly. You would have to be at the right boundary for this to matter. 2) make sure that this sequence begins on a longword boundary. There appears to be a bug in binutils which makes some of these calculations get messed up if the instruction sequence does not begin on a longword boundary. This is being investigated with the appropriate binutils folks. llvm-svn: 190966
* Debug info: Get rid of the VLA indirection hack in FastISel.Adrian Prantl2013-09-184-21/+19
| | | | | | | | Use the DIVariable::isIndirect() flag set by the frontend instead of guessing whether to set the machine location's indirection bit. Paired commit with CFE. llvm-svn: 190961
* Attempt to fix llvm-ppc64-linux2 buildbot failure by addingPreston Gurd2013-09-181-1/+1
| | | | | | -march=x86 to SLM test. llvm-svn: 190958
* Verify that llvm can generate the prefetchw instruction when the CPU isPreston Gurd2013-09-181-0/+2
| | | | | | | | Atom Silvermont. Patch by Sriram Murali. llvm-svn: 190957
* Make DynamicLibrary use ManagedStatic. This is pretty simple and should just ↵Filip Pizlo2013-09-182-28/+10
| | | | | | | | | | work as advertised - but it does have the caveat that calls to DynamicLibrary::AddSymbol will "reset" if you shutdown llvm and try to come back for seconds. This is a subtle behavior change, but I'm assuming that nobody is affected by it. llvm-svn: 190946
* More XCore TTI cleanup -- remove an unused private field flagged byChandler Carruth2013-09-181-4/+2
| | | | | | -Wunused-private-field with Clang. llvm-svn: 190941
* Name the XCore target-specific subdirectories canonically.Chandler Carruth2013-09-184-0/+0
| | | | llvm-svn: 190940
* [asan] call __asan_stack_malloc_N only if use-after-return detection is ↵Kostya Serebryany2013-09-181-1/+22
| | | | | | enabled with the run-time option llvm-svn: 190939
* A couple of tests, in llvm/test/Transforms/*/xcore, are XCore-specific. They ↵NAKAMURA Takumi2013-09-182-0/+6
| | | | | | should be excluded when XCore is not built. llvm-svn: 190938
* Target/XCore/CMakeLists.txt: Add XCoreTargetTransformInfo.cpp.NAKAMURA Takumi2013-09-181-0/+1
| | | | llvm-svn: 190937
* Prevent LoopVectorizer and SLPVectorizer running if the target has no vector ↵Robert Lytton2013-09-189-0/+172
| | | | | | | | | | registers. XCore target: Add XCoreTargetTransformInfo This is where getNumberOfRegisters() resides, which in turn returns the number of vector registers (=0). llvm-svn: 190936
* Re-add tests from r179291 which were accidentally removed by r181177.Andrea Di Biagio2013-09-181-0/+28
| | | | llvm-svn: 190934
* [SystemZ] Add unsigned compare-and-branch instructionsRichard Sandiford2013-09-1833-156/+2234
| | | | | | | | | | | | | | | For some reason I never got around to adding these at the same time as the signed versions. No idea why. I'm not sure whether this SystemZII::BranchC* stuff is useful, or whether it should just be replaced with an "is normal" flag. I'll leave that for later though. There are some boundary conditions that can be tweaked, such as preferring unsigned comparisons for equality with [128, 256), and "<= 255" over "< 256", but again I'll leave those for a separate patch. llvm-svn: 190930
* 'svn add' the test cases.Joey Gouly2013-09-185-0/+92
| | | | llvm-svn: 190929
* [ARMv8] Add CRC instructions.Joey Gouly2013-09-184-1/+96
| | | | | | Patch by Bradley Smith! llvm-svn: 190928
* Revert r190921. It broke Windows.Filip Pizlo2013-09-181-7/+25
| | | | | | I'll roll it back in when I have a chance to look at it in detail. llvm-svn: 190923
* Make DynamicLibrary use ManagedStatic. This is pretty simple and should just ↵Filip Pizlo2013-09-181-25/+7
| | | | | | | | | | work as advertised - but it does have the caveat that calls to DynamicLibrary::AddSymbol will "reset" if you shutdown llvm and try to come back for seconds. This is a subtle behavior change, but I'm assuming that nobody is affected by it. llvm-svn: 190921
* Prevent extra calls to ToggleFeature for Feature64Bit and FeatureCMOV if ↵Craig Topper2013-09-181-2/+2
| | | | | | they've already been enabled. The extra call ends up clearing the bit in FeatureBits since its a 'toggle'. Can't prove that anything was broken because of this since I don't think the FeatureBits for these are used. llvm-svn: 190920
* Fix X86 subtarget to not overwrite the autodetected features by calling ↵Craig Topper2013-09-183-1/+9
| | | | | | InitMCProcessorInfo right after detecting them. Instead add a new function that only updates the scheduling model and call that. llvm-svn: 190919
* Revert accidental commit I had to make to get the test case in PR17268 to ↵Craig Topper2013-09-181-1/+1
| | | | | | still work correctly. llvm-svn: 190917
* Lift alignment restrictions for load/store folding on ↵Craig Topper2013-09-184-13/+12
| | | | | | VINSERTF128/VEXTRACTF128. Fixes PR17268. llvm-svn: 190916
* ifndef NDEBUG-out an asserts-only constant committed in r190863David Blaikie2013-09-181-0/+2
| | | | llvm-svn: 190905
* Fix a constant folding address space place I missed.Matt Arsenault2013-09-172-3/+12
| | | | | | | | If address space 0 was smaller than the address space in a constant inttoptr/ptrtoint pair, the wrong mask size would be used. llvm-svn: 190899
* COFF: Ensure that objects produced by LLVM link with /safesehReid Kleckner2013-09-174-5/+54
| | | | | | | | | | | | | | | | | | | | Summary: We indicate that the object files are safe by emitting a @feat.00 absolute address symbol. The address is presumably interpreted as a bitfield of features that the compiler would like to enable. Bit 0 is documented in the PE COFF spec to opt in to "registered SEH", which is what /safeseh enables. LLVM's object files are safe by default because LLVM doesn't know how to produce SEH handlers. Reviewers: Bigcheese CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1691 llvm-svn: 190898
* Missed using check type enum in one placeMatt Arsenault2013-09-171-6/+6
| | | | llvm-svn: 190897
* Use function's argument instead of the global flag.Matt Arsenault2013-09-171-3/+3
| | | | | | For now it happens the argument is always the same. llvm-svn: 190896
* FileCheck refactor: use enum instead of bunch of boolsMatt Arsenault2013-09-171-76/+88
| | | | llvm-svn: 190893
* Revert the load slicing done in r190870.Quentin Colombet2013-09-172-615/+0
| | | | | | | To avoid regressions with bitfield optimizations, this slicing should take place later, like ISel time. llvm-svn: 190891
* COFF: Emit all MCSymbols rather than filtering out some of themReid Kleckner2013-09-172-20/+13
| | | | | | | | | | In particular, this means we emit non-external symbols defined to variables, such as aliases or absolute addresses. This is needed to implement /safeseh, and it appears there was some confusion about what symbols to emit previously. llvm-svn: 190888
* COFF: Remove ExportSection, which has been dead since r114823Reid Kleckner2013-09-171-5/+0
| | | | llvm-svn: 190887
* Move variable into assert to avoid unused variable warning.Eric Christopher2013-09-171-2/+1
| | | | llvm-svn: 190886
* Cleanup handling of constant function casts.Matt Arsenault2013-09-172-25/+150
| | | | | | | | | | Some of this code is no longer necessary since int<->ptr casts are no longer occur as of r187444. This also fixes handling vectors of pointers, and adds a bunch of new testcases for vectors and address spaces. llvm-svn: 190885
* [PowerPC] Add a FIXME.Bill Schmidt2013-09-171-0/+4
| | | | | | | | Documenting a design choice to generate only medium model sequences for TLS addresses at this time. Small and large code models could be supported if necessary. llvm-svn: 190883
* [PowerPC] Fix problems with large code model (PR17169).Bill Schmidt2013-09-175-16/+34
| | | | | | | | | | | | | | Large code model on PPC64 requires creating and referencing TOC entries when using the addis/ld form of addressing. This was not being done in all cases. The changes in this patch to PPCAsmPrinter::EmitInstruction() fix this. Two test cases are also modified to reflect this requirement. Fast-isel was not creating correct code for loading floating-point constants using large code model. This also requires the addis/ld form of addressing. Previously we were using the addis/lfd shortcut which is only applicable to medium code model. One test case is modified to reflect this requirement. llvm-svn: 190882
* Costmodel: Add support for horizontal vector reductionsArnold Schwaighofer2013-09-175-0/+406
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upcoming SLP vectorization improvements will want to be able to estimate costs of horizontal reductions. Add infrastructure to support this. We model reductions as a series of (shufflevector,add) tuples ultimately followed by an extractelement. For example, for an add-reduction of <4 x float> we could generate the following sequence: (v0, v1, v2, v3) \ \ / / \ \ / + + (v0+v2, v1+v3, undef, undef) \ / ((v0+v2) + (v1+v3), undef, undef) %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef> %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7 %r = extractelement <4 x float> %bin.rdx8, i32 0 This commit adds a cost model interface "getReductionCost(Opcode, Ty, Pairwise)" that will allow clients to ask for the cost of such a reduction (as backends might generate more efficient code than the cost of the individual instructions summed up). This interface is excercised by the CostModel analysis pass which looks for reduction patterns like the one above - starting at extractelements - and if it sees a matching sequence will call the cost model interface. We will also support a second form of pairwise reduction that is well supported on common architectures (haddps, vpadd, faddp). (v0, v1, v2, v3) \ / \ / (v0+v1, v2+v3, undef, undef) \ / ((v0+v1)+(v2+v3), undef, undef, undef) %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef, <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef> %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef> %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1 %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef> %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> %bin.rdx.1 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1 %r = extractelement <4 x float> %bin.rdx.1, i32 0 llvm-svn: 190876
* SLPVectorizer: Don't vectorize phi nodes that use invoke valuesArnold Schwaighofer2013-09-172-0/+74
| | | | | | | | | We can't insert an insertelement after an invoke. We would have to split a critical edge. So when we see a phi node that uses an invoke we just give up. radar://14990770 llvm-svn: 190871
* [InstCombiner] Slice a big load in two loads when the elements are next to eachQuentin Colombet2013-09-172-0/+615
| | | | | | | | | | | | | | | | | | | | | | | | | | | other in memory. The motivation was to get rid of truncate and shift right instructions that get in the way of paired load or floating point load. E.g., Consider the following example: struct Complex { float real; float imm; }; When accessing a complex, llvm was generating a 64-bits load and the imm field was obtained by a trunc(lshr) sequence, resulting in poor code generation, at least for x86. The idea is to declare that two load instructions is the canonical form for loading two arithmetic type, which are next to each other in memory. Two scalar loads at a constant offset from each other are pretty easy to detect for the sorts of passes that like to mess with loads. <rdar://problem/14477220> llvm-svn: 190870
* Remove unused code, which had been commented out.Preston Gurd2013-09-171-5/+0
| | | | llvm-svn: 190869
* Added documentation to getMemsetStores.Serge Pavlov2013-09-171-0/+18
| | | | llvm-svn: 190866
* Add llvm.x86.* intrinsics for Intel SHA ExtensionsBen Langmuir2013-09-172-14/+47
| | | | | | | | Add llvm.x86.* intrinsics for all of the Intel SHA Extensions instructions, as well as tests. Also remove mayLoad and hasSideEffects, which can be inferred from the instruction patterns. llvm-svn: 190864
* [asan] inline the calls to __asan_stack_free_* with small sizes. Yet another ↵Kostya Serebryany2013-09-171-3/+48
| | | | | | 10%-20% speedup for use-after-return llvm-svn: 190863
* [ARM] Fix the deprecation of MCR encodings that map to CP15{ISB,DSB,DMB}.Joey Gouly2013-09-173-12/+40
| | | | llvm-svn: 190862
* Bugfix for PR17099:Stepan Dyatkovskiy2013-09-172-8/+33
| | | | | | | | | | | Wrong cast operation. MergeFunctions emits Bitcast instead of pointer-to-integer operation. Patch fixes MergeFunctions::writeThunk function. It replaces unconditional Bitcast creation with "Value* createCast(...)" method, that checks operand types and selects proper instruction. See unit-test as example. llvm-svn: 190859
* AVX-512: Converted to Unix styleElena Demikhovsky2013-09-171-3070/+3070
| | | | llvm-svn: 190851
* Add AES and SHA instructions to the load folding tables.Craig Topper2013-09-171-0/+25
| | | | llvm-svn: 190850
* Fix column alignment. No functional change.Craig Topper2013-09-171-4/+4
| | | | llvm-svn: 190849
* Make a more clear AVX-512 section header that matches similar in the file.Craig Topper2013-09-171-1/+3
| | | | llvm-svn: 190843
* Implement 3 AArch64 neon instructions : umov smov ins.Kevin Qin2013-09-177-14/+771
| | | | llvm-svn: 190839
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