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* [AVR] Add the branch selection pass from the GitHub repositoryDylan McKay2017-07-056-7/+276
| | | | | | | We should rewrite this using the generic branch relaxation pass, but for the moment having this pass is better than hitting an assertion error. llvm-svn: 307109
* NFC.Gadi Haber2017-07-041-210/+835
| | | | | | | | | | | | | | | Made some updates to the half.ll test under CodeGen to make it friendly to the update_llc_test_checks .py tool as follows: 1.Removing the llc flag -asm-verbose=false 2.Grouping the multiple check-prefix directives 3.Apply update_llc_test_checks.py tool on the test This change is needed to easily update scheduling changes in an upcoming patch. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D34934 llvm-svn: 307108
* Recommit r307064, "[InstCombine] Add test cases demonstrating creation of ↵Craig Topper2017-07-041-0/+63
| | | | | | | | extra bswap instrinsic calls when when optimizing bswap and bitwise ops when the bswaps have additional uses. NFC" The test check lines have now been fixed. llvm-svn: 307106
* [ARM][test] Added test/CodeGen/ARM/ror.ll test. NFC precommit for D12833.Andrew Zhogin2017-07-041-0/+36
| | | | llvm-svn: 307103
* [X86][SSE4A] Add support for combining from non-v16i8 EXTRQI/INSERTQI shufflesSimon Pilgrim2017-07-043-39/+44
| | | | | | With the improved shuffle decoding we can now combine EXTRQI/INSERTQI shuffles from non-v16i8 vector types llvm-svn: 307099
* Fix signed/unsigned comparison warningsSimon Pilgrim2017-07-041-4/+4
| | | | llvm-svn: 307098
* [AMDGPU] Switch scalarize global loads ON by defaultAlexander Timofeev2017-07-04142-560/+790
| | | | | | Differential revision: https://reviews.llvm.org/D34407 llvm-svn: 307097
* [LoopDeletion] NFC: Add loop being analyzed debug statementAnna Thomas2017-07-041-0/+2
| | | | llvm-svn: 307096
* [X86][SSE4A] Generalized EXTRQI/INSERTQI shuffle decodesSimon Pilgrim2017-07-044-31/+41
| | | | | | The existing decodes only worked for v16i8 vectors, this adds support for any 128-bit vector llvm-svn: 307095
* fix trivial typos in comments; NFCHiroshi Inoue2017-07-043-3/+3
| | | | llvm-svn: 307094
* [globalisel][tablegen] Fix the modules build after r307079Daniel Sanders2017-07-041-0/+1
| | | | | | Exclude InstructionSelectorImpl.h since DEBUG_TYPE may vary between includes. llvm-svn: 307093
* [DAGCombiner] Intermediate variables in visitRotate promoted to the ↵Andrew Zhogin2017-07-041-6/+9
| | | | | | function's begin. NFC precommit for D12833. llvm-svn: 307091
* [globalisel][tablegen] Fix release builds after r307079Daniel Sanders2017-07-042-3/+8
| | | | | | | | | Using NumPatternEmitted as a unique id for the tables is not valid on release builds since the counters don't count in that case. Also fix an unused variable warning. llvm-svn: 307088
* [FastISel] Move gc intrinsic test to X86 directoryAnna Thomas2017-07-041-0/+2
| | | | | | | | | Move from generic to X86 directory since gc intrinsics only supposed in X86 64 bit. Add target triple as well. Fixes build failure in i686-linux-RA caused by rL307084. llvm-svn: 307086
* Fix dangling StringRefs found by clang-tidy misc-dangling-handle check.Alexander Kornienko2017-07-042-4/+8
| | | | llvm-svn: 307085
* [FastISel][SelectionDAG]Teach fastISel about GC intrinsicsAnna Thomas2017-07-042-1/+60
| | | | | | | | | | | | | | | | | | | | | | | Summary: We are crashing in LLC at O0 when gc intrinsics are present in the block. The reason being FastISel performs basic block ISel by modifying GC.relocates to be the first instruction in the block. This can cause us to visit the GC relocate before it's corresponding GC.statepoint is visited, which is incorrect. When we lower the statepoint, we record the base and derived pointers, along with the gc.relocates. After this we can visit the gc.relocate. This patch avoids fastISel from incorrectly creating the block with gc.relocate as the first instruction. Reviewers: qcolombet, skatkov, qikon, reames Reviewed by: skatkov Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34421 llvm-svn: 307084
* [AMDGPU] Fix latency of MIMG instructionsMarek Olsak2017-07-041-0/+1
| | | | | | Patch by cwabbott (Connor Abbott). llvm-svn: 307081
* NFC. Removed mention of missing script from build_docker_image.sh.Ilya Biryukov2017-07-041-1/+3
| | | | llvm-svn: 307080
* [globalisel][tablegen] Partially fix compile-time regressions by converting ↵Daniel Sanders2017-07-048-519/+1062
| | | | | | | | | | | | | | | | | | | | | | matcher to state-machine(s) Summary: Replace the matcher if-statements for each rule with a state-machine. This significantly reduces compile time, memory allocations, and cumulative memory allocation when compiling AArch64InstructionSelector.cpp.o after r303259 is recommitted. The following patches will expand on this further to fully fix the regressions. Reviewers: rovka, ab, t.p.northover, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: vitalybuka, aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33758 llvm-svn: 307079
* [LoopDeletion] NFC: Add debug statements to the optimizationAnna Thomas2017-07-041-13/+24
| | | | | | | We have a DEBUG option for loop deletion, but no related debug messages. Added some debug messages to state why loop deletion failed. llvm-svn: 307078
* fix trivial typos in comments; NFCHiroshi Inoue2017-07-045-5/+5
| | | | llvm-svn: 307075
* [X86] Add combine tests for vector rotatesSimon Pilgrim2017-07-041-0/+83
| | | | | | Reference tests for D12833 llvm-svn: 307073
* Revert r307064, "[InstCombine] Add test cases demonstrating creation of ↵NAKAMURA Takumi2017-07-041-63/+0
| | | | | | | | extra bswap instrinsic calls when when optimizing bswap and bitwise ops when the bswaps have additional uses. NFC" Seems confused between %tmpN and unnamed %N to give same name. llvm-svn: 307070
* llvm/ExecutionEngine/Orc/ObjectTransformLayer.h: Add <memory> to appease ↵NAKAMURA Takumi2017-07-041-0/+1
| | | | | | libstdc++'s std::shared_ptr. llvm-svn: 307069
* NFC commit.Gadi Haber2017-07-041-25/+26
| | | | | | | | | | | | Converting the Codegen test "extractelement-legalization-store-ordering.ll" to be "update_llc_test_checks" friendly. The changes to the test are needed for an upcoming scheduling patch. Reviewers: zvi, RKSimon Differential Revision: https://reviews.llvm.org/D34935 llvm-svn: 307066
* [InstCombine] Add TODOs for a couple things that should maybe be in ↵Craig Topper2017-07-041-1/+3
| | | | | | InstSimplify instead. NFC llvm-svn: 307065
* [InstCombine] Add test cases demonstrating creation of extra bswap ↵Craig Topper2017-07-041-0/+63
| | | | | | | | instrinsic calls when when optimizing bswap and bitwise ops when the bswaps have additional uses. NFC I assume bswap intrinsics are somewhat costly so we should be making sure we are getting rid of them not creating more. llvm-svn: 307064
* [tablegen] Avoid creating a temporary vector in getInstructionCaseAlexander Shaposhnikov2017-07-041-8/+6
| | | | | | | | | | | | | Record::getValues returns ArrayRef which has a cast operator to std::vector, as a result a temporary vector is created if the type of the variable is const std::vector& that is suboptimal in this case. Differential revision: https://reviews.llvm.org/D34969 Test plan: make check-all llvm-svn: 307063
* [X86] Add comment string for broadcast loads from the constant pool.Craig Topper2017-07-047-676/+1615
| | | | | | | | | | | | | | | | | Summary: When broadcasting from the constant pool its useful to print out the final vector similar to what we do for normal moves from the constant pool. I changed only a couple tests that were broadcast focused. One of them had been previously hand tweaked after running the script so that it could check the constant pool declaration. But I think this patch makes that unnecessary now since we can check the comment instead. Reviewers: spatel, RKSimon, zvi Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34923 llvm-svn: 307062
* [llvm] Revert "[tablegen] Avoid creating a temporary vector in ↵Alexander Shaposhnikov2017-07-041-1/+4
| | | | | | | | | getInstructionCase" Revert rL307059 because of the incorrect commit message & patch, will recommit later. llvm-svn: 307061
* [X86] Add RDRAND feature to GLM CPUCraig Topper2017-07-041-0/+1
| | | | | | | | | | | | | | Summary: I believe this should be supported on GLM since RDSEED is. Reviewers: m_zuckerman, zvi, RKSimon Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34828 llvm-svn: 307060
* [tablegen] Avoid creating a temporary vector in getInstructionCaseAlexander Shaposhnikov2017-07-041-4/+1
| | | | | | | | | | | | | Record::getValues returns ArrayRef which has a cast operator to std::vector, as a result a temporary vector is created if the type of the variable is const std::vector& that was suboptimal in this case. Differential revision: https://reviews.llvm.org/D34969 Test plan: make check-all llvm-svn: 307059
* [Orc] Remove the memory manager argument to addModule, and de-templatize theLang Hames2017-07-0420-185/+133
| | | | | | | | | | | | | | | | symbol resolver argument. De-templatizing the symbol resolver is part of the ongoing simplification of ORC layer API. Removing the memory management argument (and delegating construction of memory managers for RTDyldObjectLinkingLayer to a functor passed in to the constructor) allows us to build JITs whose base object layers need not be compatible with RTDyldObjectLinkingLayer's memory mangement scheme. For example, a 'remote object layer' that sends fully relocatable objects directly to the remote does not need a memory management scheme at all (that will be handled by the remote). llvm-svn: 307058
* [AVR] Fix bug which caused assertion errors for some FRMIDX instructionsDylan McKay2017-07-042-3/+41
| | | | | | | | | | | | | Previously, if a basic block ended with a FRMIDX instruction, we would end up doing something like this. *std::next(MBB.end()) Which would hit an error: "Assertion `!NodePtr->isKnownSentinel()' failed." llvm-svn: 307057
* [AVR] Add a missing clobber declaration to LPMWDylan McKay2017-07-041-6/+6
| | | | llvm-svn: 307056
* [DAG] Fixed predicate for determining when two frame indicesNirav Dave2017-07-041-5/+5
| | | | | | addresses are comparable. NFCI. llvm-svn: 307055
* Revert r307026, "[AMDGPU] Switch scalarize global loads ON by default"NAKAMURA Takumi2017-07-04141-789/+559
| | | | | | | | | It broke a testcase. Failing Tests (1): LLVM :: CodeGen/AMDGPU/alignbit-pat.ll llvm-svn: 307054
* [legalize-types] Clean up softening machinery.Anton Yartsev2017-07-045-42/+144
| | | | | | | | The patch makes SoftenFloatResult/Operand logic just the same as all other legalization routines have: SoftenFloatResult() now fills the SoftenFloats map and SoftenFloatOperand() perform all needed replacements. This prevents softening mashinery from leaving stale entries in SoftenFloats map (that resulted in errors during the legalize type checking) and clarifies softening. The patch replaces https://reviews.llvm.org/D29265. Differential Revision: https://reviews.llvm.org/D31946 llvm-svn: 307053
* [X86][SSE4A] Add support for combining from EXTRQI/INSERTQI shufflesSimon Pilgrim2017-07-033-18/+31
| | | | llvm-svn: 307048
* MathExtras UnitTest: Assert that isPowerOf2(0) is false. NFC.Zvi Rackover2017-07-031-0/+2
| | | | | | | | | | | | | | | | | Summary: This is a follow-up on D34077. Elena observed that the correctness of the code relies on isPowerOf2(0) returning false. Adding a test to cover this corner-case. Reviewers: delena, davide, craig.topper Reviewed By: davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34939 llvm-svn: 307046
* [X86][SSE4A] Add SSE4A shuffle tests on pre-SSSE3 hardwareSimon Pilgrim2017-07-031-0/+71
| | | | llvm-svn: 307042
* [X86][SSE4A] Test SSE4A shuffle combining on SSE42 capable target as wellSimon Pilgrim2017-07-031-17/+36
| | | | llvm-svn: 307038
* DAGCombine: Combine BUILD_VECTOR to TRUNCATEZvi Rackover2017-07-036-557/+285
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a combine for creating a truncate to replace a build_vector composed of extracts with indices that form a stride-2^N series. Example: v8i32 V = ... v4i32 build_vector((extract_elt V, 0), (extract_elt V, 2), (extract_elt V, 4), (extract_elt V, 6)) --> v4i32 truncate (bitcast V to v4i64) Related discussion in llvm-dev about canonicalizing shuffles to truncates in LLVM IR: http://lists.llvm.org/pipermail/llvm-dev/2017-January/108936.html. Reviewers: spatel, RKSimon, efriedma, igorb, craig.topper, wolfgangp, delena Reviewed By: delena Subscribers: guyblank, delena, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D34077 llvm-svn: 307036
* [LoopInterchange] Add more debug messages to currentLimitations(). Florian Hahn2017-07-031-10/+34
| | | | | | | | | | | | | | Summary: This makes it easier to find out which limitation prevented this pass from doing its work. Reviewers: karthikthecool, mzolotukhin, efriedma, mcrosier Reviewed By: mcrosier Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D34940 llvm-svn: 307035
* [x86] auto-generate complete checks for tests; NFCSanjay Patel2017-07-034-155/+162
| | | | | | | These all used 'CHECK-NOT' which isn't necessary if we have complete checks. There were also over-specifications in the RUN params such as CPU model. llvm-svn: 307033
* Fixed argument parsing in docker scripts.Ilya Biryukov2017-07-031-0/+1
| | | | llvm-svn: 307031
* [x86] auto-generate complete checks for tests; NFCSanjay Patel2017-07-034-219/+539
| | | | | | | These all used 'CHECK-NOT' which isn't necessary if we have complete checks. There were also several over-specifications in the RUN params such as CPU model or OS requirement llvm-svn: 307028
* [X86][SSE4A] Add tests showing missed opportunities to combine ↵Simon Pilgrim2017-07-031-0/+80
| | | | | | EXTRQI/INSERTQI shuffles llvm-svn: 307027
* [AMDGPU] Switch scalarize global loads ON by defaultAlexander Timofeev2017-07-03141-559/+789
| | | | | | Differential revision: https://reviews.llvm.org/D34407 llvm-svn: 307026
* [x86] auto-generate complete checks for tests; NFCSanjay Patel2017-07-034-337/+337
| | | | | | These all used 'CHECK-NOT' which isn't necessary if we have complete checks. llvm-svn: 307024
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