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* Fix a problem with fast-isel return values introduced in r134018.Jakob Stoklund Olesen2011-06-302-2/+27
| | | | | | | | | We would put the return value from long double functions in the wrong register. This fixes gcc.c-torture/execute/conversion.c llvm-svn: 134205
* Refact ARM Thumb1 tMOVr instruction family.Jim Grosbach2011-06-309-86/+26
| | | | | | | | | | Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions into tMOVr. There's no need to keep them separate. Giving the tMOVr instruction the proper GPR register class for its operands is sufficient to give the register allocator enough information to do the right thing directly. llvm-svn: 134204
* Add support for the 'h' constraint.Eric Christopher2011-06-303-1/+17
| | | | | | Part of rdar://9119939 llvm-svn: 134203
* Add target a target hook to get the register number used by the compact unwindBill Wendling2011-06-304-0/+29
| | | | | | | encoding for the registers it knows about. Return -1 if it can't handle that register. llvm-svn: 134202
* Revert my previous patch while I debug llvm-gcc bootstrap.Rafael Espindola2011-06-301-95/+10
| | | | llvm-svn: 134201
* Add one more comment to the FDE verbose asm output.Bill Wendling2011-06-301-0/+1
| | | | llvm-svn: 134200
* Don't give up on coalescing A and B when we findRafael Espindola2011-06-301-10/+95
| | | | | | | | | | | | A = X B = X Instead, proceed as if we had found A = X B = A llvm-svn: 134199
* Add a convenience typedef for std::pair<unsigned, const TargetRegisterClass*>.Eric Christopher2011-06-301-7/+8
| | | | | | | | No functional change. Part of rdar://9119939 llvm-svn: 134198
* Thumb1 register to register MOV instruction is predicable.Jim Grosbach2011-06-3010-59/+67
| | | | | | | | | Fix a FIXME and allow predication (in Thumb2) for the T1 register to register MOV instructions. This allows some better codegen with if-conversion (as seen in the test updates), plus it lays the groundwork for pseudo-izing the tMOVCC instructions. llvm-svn: 134197
* Add comments to the FDE.Bill Wendling2011-06-301-5/+13
| | | | llvm-svn: 134196
* Add more comments to the ASM output for the CIE's "moves".Bill Wendling2011-06-301-1/+20
| | | | llvm-svn: 134194
* Tweak error messages to match GCC. Should fix gcc.target/i386/pr30848.cJakob Stoklund Olesen2011-06-301-3/+3
| | | | llvm-svn: 134193
* Add comments to the ASM output to help understand the compact unwind and CIE ↵Bill Wendling2011-06-301-6/+61
| | | | | | tables. llvm-svn: 134191
* Create a isFullCopy predicate.Rafael Espindola2011-06-302-5/+4
| | | | llvm-svn: 134189
* Add r134057 back, but splice the predecessor after the successors phiRafael Espindola2011-06-305-11/+68
| | | | | | | | | nodes. Original message: Let simplify cfg simplify bb with only debug and lifetime intrinsics. llvm-svn: 134182
* Pseudo-ize the Thumb tTPsoft instruction.Jim Grosbach2011-06-304-28/+7
| | | | | | | It's just a call to a special helper function. Get rid of the T2 variant entirely, as it's identical to the Thumb1 version. llvm-svn: 134178
* indvars -disable-iv-rewrite: handle cloning binary operators that cannot ↵Andrew Trick2011-06-302-7/+45
| | | | | | overflow. llvm-svn: 134177
* Pseudo-ize the t2LDMIA_RET instruction.Jim Grosbach2011-06-303-20/+13
| | | | | | | | It's just a t2LDMIA_UPD instruction with extra codegen properties, so it doesn't need the encoding information. As a side-benefit, we now correctly recognize for instruction printing as a 'pop' instruction. llvm-svn: 134173
* Pseudo-ize the Thumb tPOP_RET instruction.Jim Grosbach2011-06-303-11/+12
| | | | | | | It's just a tPOP instruction with additional code-gen properties, so it doesn't need encoding information. llvm-svn: 134172
* Remove dead code.Rafael Espindola2011-06-301-88/+0
| | | | llvm-svn: 134148
* The enum was moved to ISDOpcodes.h.Duncan Sands2011-06-301-1/+1
| | | | llvm-svn: 134134
* Kill dead code.Jim Grosbach2011-06-301-1/+0
| | | | llvm-svn: 134131
* Size reducing SP adjusting t2ADDri needs to check predication.Jim Grosbach2011-06-301-1/+4
| | | | | | | tADDrSPi is not predicable, so we can't size-reduce a t2ADDri to it if the predicate is anything other than "always." llvm-svn: 134130
* Fix ARMSubtarget feature parsing.Evan Cheng2011-06-301-10/+7
| | | | llvm-svn: 134129
* Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-3068-236/+271
| | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! llvm-svn: 134127
* Recognize the xstorerng alias for VIA PadLock's xstore instruction.Joerg Sonnenberger2011-06-302-0/+6
| | | | llvm-svn: 134126
* Reapply r134047 now that the world is ready for it.Jakob Stoklund Olesen2011-06-303-138/+291
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch will sometimes choose live range split points next to interference instead of always splitting next to a register point. That means spill code can now appear almost anywhere, and it was necessary to fix code that didn't expect that. The difficult places were: - Between a CALL returning a value on the x87 stack and the corresponding FpPOP_RETVAL (was FpGET_ST0). Probably also near x87 inline assembly, but that didn't actually show up in testing. - Between a CALL popping arguments off the stack and the corresponding ADJCALLSTACKUP. Both are fixed now. The only place spill code can't appear is after terminators, see SplitAnalysis::getLastSplitPoint. Original commit message: Rewrite RAGreedy::splitAroundRegion, now with cool ASCII art. This function has to deal with a lot of special cases, and the old version got it wrong sometimes. In particular, it would sometimes leave multiple uses in the stack interval in a single block. That causes bad code with multiple reloads in the same basic block. The new version handles block entry and exit in a single pass. It first eliminates all the easy cases, and then goes on to create a local interval for the blocks with difficult interference. Previously, we would only create the local interval for completely isolated blocks. It can happen that the stack interval becomes completely empty because we could allocate a register in all edge bundles, and the new local intervals deal with the interference. The empty stack interval is harmless, but we need to remove a SplitKit assertion that checks for empty intervals. llvm-svn: 134125
* indvars -disable-iv-rewrite: handle an edge case involving identity phis.Andrew Trick2011-06-302-10/+40
| | | | llvm-svn: 134124
* Remove getRegClassForInlineAsmConstraint and all dependencies.Eric Christopher2011-06-303-115/+0
| | | | | | Fixes rdar://9643582 llvm-svn: 134123
* Make sure we use the correct register class here since we'll need toEric Christopher2011-06-301-1/+2
| | | | | | care about spill values. llvm-svn: 134122
* Fix a small thinko for constant i64 lock/orq optimization where weEric Christopher2011-06-302-2/+22
| | | | | | | | we didn't have an opcode for 64-bit constant or expressions. Fixes rdar://9692967 llvm-svn: 134121
* * Use the proper size to output the range size.Bill Wendling2011-06-301-1/+8
| | | | | | * Rough in the compact encoding part. llvm-svn: 134119
* Stupid error: If the LSDA and Personality functions aren't there, emit 0 insteadBill Wendling2011-06-291-10/+8
| | | | | | of the encoding. llvm-svn: 134117
* Revert r133953 for now.Devang Patel2011-06-294-148/+0
| | | | llvm-svn: 134116
* We don't want to use relocations inside the compact unwind section. Just use theBill Wendling2011-06-291-4/+19
| | | | | | symbols instead. llvm-svn: 134115
* Remove redundant Thumb2 ADD/SUB SP instruction definitions.Jim Grosbach2011-06-297-118/+56
| | | | | | | | | | Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the stack pointer. It can just use the normal add-register-immediate encoding since it can use all registers as a source, not just R0-R7. The extra instruction definitions are just duplicates of the normal instructions with the (not well enforced) constraint that the source register was SP. llvm-svn: 134114
* Always adjust the stack pointer immediately after the call.Jakob Stoklund Olesen2011-06-291-0/+7
| | | | | | | | | | | | | | | | | | | Some x86-32 calls pop values off the stack, and we need to readjust the stack pointer after the call. This happens when ADJCALLSTACKUP is eliminated. It could happen that spill code was inserted between the CALL and ADJCALLSTACKUP instructions, and we would compute wrong stack pointer offsets for those frame index references. Fix this by inserting the stack pointer adjustment immediately after the call instead of where the ADJCALLSTACKUP instruction was erased. I don't have a test case since we don't currently insert code in that position. We will soon, though. I am testing a regalloc patch that didn't work on Linux because of this. llvm-svn: 134113
* indvars -disable-iv-rewrite: insert new trunc instructions carefully.Andrew Trick2011-06-292-15/+52
| | | | llvm-svn: 134112
* Added IRBuilder::SetInsertPoint(Use) to find a valid insertion pointAndrew Trick2011-06-291-0/+19
| | | | | | that dominates the given Use. llvm-svn: 134111
* whitespaceAndrew Trick2011-06-291-8/+8
| | | | llvm-svn: 134110
* In the ARM global merging pass, allow extraneous alignment specifiers. This passCameron Zwarich2011-06-292-2/+16
| | | | | | | | already makes the assumption, which is correct on ARM, that a type's alignment is less than its alloc size. This improves codegen with Clang (which inserts a lot of extraneous alignment specifiers) and fixes <rdar://problem/9695089>. llvm-svn: 134106
* ARM RSCS* don't need explicit TableGen decoder checks.Jim Grosbach2011-06-291-4/+0
| | | | | | | They've been pseudos for a while now, so the decoder will never see them in the first place. llvm-svn: 134101
* IndentationEvan Cheng2011-06-291-1/+1
| | | | llvm-svn: 134100
* Remove getRegClassForInlineAsmConstraint from the ARM port.Eric Christopher2011-06-292-59/+15
| | | | | | Part of rdar://9643582 llvm-svn: 134095
* Remove todo.Eric Christopher2011-06-291-2/+0
| | | | llvm-svn: 134094
* make compose and isMoveInstr static functions.Rafael Espindola2011-06-292-16/+10
| | | | llvm-svn: 134093
* Refactor away tSpill and tRestore pseudos in ARM backend.Jim Grosbach2011-06-296-39/+9
| | | | | | | The tSpill and tRestore instructions are just copies of the tSTRspi and tLDRspi instructions, respectively. Just use those directly instead. llvm-svn: 134092
* Add a TODO for the Alpha port inline asm constraints.Eric Christopher2011-06-291-0/+2
| | | | llvm-svn: 134089
* Move Alpha from getRegClassForInlineAsmConstraint toEric Christopher2011-06-292-32/+14
| | | | | | | | getRegForInlineAsmConstraint. Part of rdar://9643582 llvm-svn: 134088
* Update comment for getRegForInlineAsmConstraint for Mips.Eric Christopher2011-06-291-3/+3
| | | | llvm-svn: 134087
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