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* 1. Use SubtargetFeatures in llc/lli.Jim Laskey2005-09-0125-40/+188
| | | | | | | | 2. Propagate feature "string" to all targets. 3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget. llvm-svn: 23192
* This new class provides support for platform specific "features". The intentJim Laskey2005-09-012-0/+318
| | | | | | | is to manage processor specific attributes from the command line. See examples of use in llc/lli and PowerPCTargetSubtarget. llvm-svn: 23191
* Implement dynamic allocas correctly. In particular, because we were copyingChris Lattner2005-09-011-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | directly out of R1 (without using a CopyFromReg, which uses a chain), multiple allocas were getting CSE'd together, producing bogus code. For this: int %foo(bool %X, int %A, int %B) { br bool %X, label %T, label %F F: %G = alloca int %H = alloca int store int %A, int* %G store int %B, int* %H %R = load int* %G ret int %R T: ret int 0 } We were generating: _foo: stwu r1, -16(r1) stw r31, 4(r1) or r31, r1, r1 stw r1, 12(r31) cmpwi cr0, r3, 0 bne cr0, .LBB_foo_2 ; T .LBB_foo_1: ; F li r2, 16 subf r2, r2, r1 ;; One alloca or r1, r2, r2 or r3, r1, r1 or r1, r2, r2 or r2, r1, r1 stw r4, 0(r3) stw r5, 0(r2) lwz r3, 0(r3) lwz r1, 12(r31) lwz r31, 4(r31) lwz r1, 0(r1) blr .LBB_foo_2: ; T li r3, 0 lwz r1, 12(r31) lwz r31, 4(r31) lwz r1, 0(r1) blr Now we generate: _foo: stwu r1, -16(r1) stw r31, 4(r1) or r31, r1, r1 stw r1, 12(r31) cmpwi cr0, r3, 0 bne cr0, .LBB_foo_2 ; T .LBB_foo_1: ; F or r2, r1, r1 li r3, 16 subf r2, r3, r2 ;; Alloca 1 or r1, r2, r2 or r2, r1, r1 or r6, r1, r1 subf r3, r3, r6 ;; Alloca 2 or r1, r3, r3 or r3, r1, r1 stw r4, 0(r2) stw r5, 0(r3) lwz r3, 0(r2) lwz r1, 12(r31) lwz r31, 4(r31) lwz r1, 0(r1) blr .LBB_foo_2: ; T li r3, 0 lwz r1, 12(r31) lwz r31, 4(r31) lwz r1, 0(r1) blr This fixes Povray and SPASS with the dag isel, the last two failing cases. Tommorow we will hopefully turn it on by default! :) llvm-svn: 23190
* Fix a bug where we were useing HA to get the high part, which seems like itChris Lattner2005-09-011-11/+10
| | | | | | | | | | could cause a miscompile. Fixing this didn't fix the two programs that fail though. :( This also changes the implementation to follow the pattern selector more closely, causing us to select 0 to li instead of lis. llvm-svn: 23189
* Do not select the operands being passed into SelectCC. IT does this itselfChris Lattner2005-09-011-4/+2
| | | | | | and selecting early prevents folding immediates into the cmpw* instructions llvm-svn: 23188
* It is NDEBUG not _NDEBUGChris Lattner2005-09-012-3/+3
| | | | llvm-svn: 23186
* Add the rest of the currently implemented visit routines to the switchNate Begeman2005-09-011-22/+36
| | | | | | statement in visit(). llvm-svn: 23185
* First pass at the DAG Combiner. It isn't used anywhere yet, but it shouldNate Begeman2005-09-012-0/+1062
| | | | | | | be mostly functional. It currently has all folds from SelectionDAG.cpp that do not involve a condition code. llvm-svn: 23184
* Add regression test for efficient codegen of i32 x i32 -> hi32(i64) asNate Begeman2005-09-011-0/+17
| | | | | | mulhs. llvm-svn: 23183
* remove an inappropriate commentChris Lattner2005-08-311-2/+1
| | | | llvm-svn: 23182
* If a function has live ins/outs, print themChris Lattner2005-08-311-1/+23
| | | | llvm-svn: 23181
* Move FCTIWZ handling out of the instruction selectors and into legalization,Chris Lattner2005-08-314-64/+70
| | | | | | getting them out of the business of making stack slots. llvm-svn: 23180
* Remove dead codeChris Lattner2005-08-312-75/+0
| | | | llvm-svn: 23179
* Move SHL,SHR i64 -> legalizerChris Lattner2005-08-311-2/+57
| | | | llvm-svn: 23178
* Remove code that is now dead from the pattern isel.Chris Lattner2005-08-311-28/+2
| | | | llvm-svn: 23177
* lower sra_parts on the dag, implementing it for the dag isel, and exposingChris Lattner2005-08-311-0/+28
| | | | | | the ops to dag optimization. llvm-svn: 23176
* Allow targets to custom expand shifts that are too large for their registersChris Lattner2005-08-311-0/+39
| | | | llvm-svn: 23173
* Add a testcase for nate's patchChris Lattner2005-08-311-0/+12
| | | | llvm-svn: 23172
* add assert zext/sext to the dag iselChris Lattner2005-08-311-0/+3
| | | | llvm-svn: 23171
* Handle AssertSext/AssertZext nodes, fixing the regressions last night.Chris Lattner2005-08-311-0/+4
| | | | llvm-svn: 23170
* Fix VC++ precedence warningsJeff Cohen2005-08-311-2/+2
| | | | llvm-svn: 23169
* Enable generation of AssertSext and AssertZext in the PPC backend.Nate Begeman2005-08-311-2/+7
| | | | llvm-svn: 23168
* Fix 'ret long' to return the high and lo parts in the right registers. ThisChris Lattner2005-08-311-9/+7
| | | | | | fixes crafty and probably others. llvm-svn: 23167
* Sigh, not my day. Fix typo.Nate Begeman2005-08-311-1/+1
| | | | llvm-svn: 23166
* Fix a mistake in my previous patch pointed out by sabre; the AssertZextNate Begeman2005-08-311-2/+3
| | | | | | case in MaskedValueIsZero was wrong. llvm-svn: 23165
* Remove some unnecessary casts, and add the AssertZext case toNate Begeman2005-08-311-2/+3
| | | | | | MaskedValueIsZero. llvm-svn: 23164
* Add support for count trailing zeroes, and population count. These areNate Begeman2005-08-311-5/+37
| | | | | | needed for folding constants in the upcoming dag combiner. llvm-svn: 23163
* now that physregs can exist in the same dag with multiple types, remove someChris Lattner2005-08-301-27/+8
| | | | | | ugly hacks llvm-svn: 23162
* Allow physregs to occur in the dag with multiple types. Though I don't ↵Chris Lattner2005-08-301-12/+8
| | | | | | | | likethis, it is a requirement on PPC, which can have an f32 value in r3 at onepoint in a function and a f64 value in r3 at another point. :( This fixes compilation of mesa llvm-svn: 23161
* Allow physregs to occur in the dag with multiple types. Though I don't likeChris Lattner2005-08-301-1/+1
| | | | | | | this, it is a requirement on PPC, which can have an f32 value in r3 at one point in a function and a f64 value in r3 at another point. :( llvm-svn: 23160
* Fix type mismatches when passing f32 values to callsChris Lattner2005-08-301-2/+7
| | | | llvm-svn: 23159
* When checking the fixed intervals, don't forget to check for register aliases.Chris Lattner2005-08-301-5/+11
| | | | | | This fixes PR621 and Regression/CodeGen/X86/2005-08-30-RegAllocAliasProblem.ll llvm-svn: 23158
* new testcase corresponding to PR621Chris Lattner2005-08-301-0/+17
| | | | llvm-svn: 23157
* The dag isel misses both of these, the pattern isel just misses the secondChris Lattner2005-08-301-0/+13
| | | | | | one. TODO :) llvm-svn: 23156
* Fix some indentation (first hunks).Chris Lattner2005-08-301-30/+20
| | | | | | | | | | | | | | | | | | | | | Remove code (last hunk) that miscompiled immediate and's, such as and uint %tmp.30, 4294958079 into andi. r8, r8, 56319 andis. r8, r8, 65535 instead of: li r9, -9217 and r8, r8, r9 The first always generates zero. This fixes espresso. llvm-svn: 23155
* Fix a problem Nate found where we swapped the operands of SHL/SHR_PARTS. ThisChris Lattner2005-08-301-4/+4
| | | | | | fixes fourinarow llvm-svn: 23153
* codegen ADD_PARTS correctly: put the results in the right registers! ThisChris Lattner2005-08-301-1/+1
| | | | | | fixes fhourstones llvm-svn: 23152
* Fix FreeBench/fourinarow with the dag isel, by not adding a bogus resultChris Lattner2005-08-301-4/+1
| | | | | | to SHIFT_PARTS nodes llvm-svn: 23151
* add operands in the right order, fixing McCat/18-imp with the dag iselChris Lattner2005-08-301-3/+3
| | | | llvm-svn: 23150
* Fix a miscompile of PtrDist/bc. Sign extending bools is not the right thing,Chris Lattner2005-08-301-1/+4
| | | | | | at least tends to expose problems elsewhere. llvm-svn: 23149
* Remove a bogus piece of my AssertSext/AssertZext patch. oops.Nate Begeman2005-08-301-2/+0
| | | | llvm-svn: 23148
* Add support for AssertSext and AssertZext, folding other extensions withNate Begeman2005-08-302-9/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | them. This allows for elminination of redundant extends in the entry blocks of functions on PowerPC. Add support for i32 x i32 -> i64 multiplies, by recognizing when the inputs to ISD::MUL in ExpandOp are actually just extended i32 values and not real i64 values. this allows us to codegen int mulhs(int a, int b) { return ((long long)a * b) >> 32; } as: _mulhs: mulhw r3, r4, r3 blr instead of: _mulhs: mulhwu r2, r4, r3 srawi r5, r3, 31 mullw r5, r4, r5 add r2, r2, r5 srawi r4, r4, 31 mullw r3, r4, r3 add r3, r2, r3 blr with a similar improvement on x86. llvm-svn: 23147
* Add AssertSext, AssertZext nodes for targets that pass arguments inNate Begeman2005-08-301-0/+7
| | | | | | | registers, and the incoming values have already been zero or sign extended from the appopriate type to the register width. llvm-svn: 23146
* Name this variable to be what it really is!Chris Lattner2005-08-301-4/+4
| | | | llvm-svn: 23145
* Handle CopyToReg nodes with flag operands correctlyChris Lattner2005-08-301-1/+6
| | | | llvm-svn: 23144
* Make sure the selector emits register register copies with flag operandsChris Lattner2005-08-301-10/+20
| | | | | | | | | linking them to calls when appropriate, this prevents the scheduler from pulling these copies away from the call. This fixes Ptrdist/yacr2 llvm-svn: 23143
* add some method variantsChris Lattner2005-08-301-0/+39
| | | | llvm-svn: 23142
* The first operand to AND does not always have more than two operands. ThisChris Lattner2005-08-301-1/+2
| | | | | | fixes MediaBench/toast with the dag selector llvm-svn: 23141
* Fix a bug in my patch for legalizing to fsel. It cannot handle seteq/setne,Chris Lattner2005-08-301-0/+4
| | | | | | | which I failed to include when I moved the code over. This fixes MallocBench/gs. llvm-svn: 23140
* emit FMR instructions to convert f64<->f32 instructions, so things likeChris Lattner2005-08-301-8/+15
| | | | | | STOREs, know the right type to store. llvm-svn: 23139
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