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* [DAGCombiner][AMDGPU][X86] Turn cttz/ctlz into ↵Craig Topper2018-02-063-12/+16
| | | | | | | | | | | | cttz_zero_undef/ctlz_zero_undef if we can prove the input is never zero X86 currently has a late DAG combine after cttz/ctlz are turned into BSR+BSF+CMOV to detect this and remove the CMOV. But we should be able to do this much earlier and avoid creating the cmov all together. For the changed AMDGPU test case it appears that previously the i8 cttz was type legalized to i16 which introduced an OR with 256 in order to limit the result to 8 on the widened type. At this point the result is known to never be zero, but nothing checked that. Then operation legalization is told to promote all i16 cttz to i32. This introduces an extend and a truncate and another OR with 65536 to limit the result to 16. With the DAG combiner change we are able to prevent the creation of the second OR since the opcode will have been changed to cttz_zero_undef after the first OR. I the lack of the OR caused the instruction to change to v_ffbl_b32_sdwa Differential Revision: https://reviews.llvm.org/D42985 llvm-svn: 324427
* Add DWARF for discriminated unionsAdrian Prantl2018-02-0619-56/+380
| | | | | | | | | | | | | | | | | | | | | | | | | n Rust, an enum that carries data in the variants is, essentially, a discriminated union. Furthermore, the Rust compiler will perform space optimizations on such enums in some situations. Previously, DWARF for these constructs was emitted using a hack (a magic field name); but this approach stopped working when more space optimizations were added in https://github.com/rust-lang/rust/pull/45225. This patch changes LLVM to allow discriminated unions to be represented in DWARF. It adds createDiscriminatedUnionType and createDiscriminatedMemberType to DIBuilder and then arranges for this to be emitted using DWARF's DW_TAG_variant_part and DW_TAG_variant. Note that DWARF requires that a discriminated union be represented as a structure with a variant part. However, as Rust only needs to emit pure discriminated unions, this is what I chose to expose on DIBuilder. Patch by Tom Tromey! Differential Revision: https://reviews.llvm.org/D42082 llvm-svn: 324426
* Place undefined globals in .bss instead of .dataEli Friedman2018-02-063-3/+30
| | | | | | | | | | | | | | | | | | | | | | Following up on the discussion from http://lists.llvm.org/pipermail/llvm-dev/2017-April/112305.html, undef values are now placed in the .bss as well as null values. This prevents undef global values taking up potentially huge amounts of space in the .data section. The following two lines now both generate equivalent .bss data: @vals1 = internal unnamed_addr global [20000000 x i32] zeroinitializer, align 4 @vals2 = internal unnamed_addr global [20000000 x i32] undef, align 4 ; previously unaccounted for This is primarily motivated by the corresponding issue in the Rust compiler (https://github.com/rust-lang/rust/issues/41315). Differential Revision: https://reviews.llvm.org/D41705 Patch by varkor! llvm-svn: 324424
* [LivePhysRegs] Fix handling of return instructions.Eli Friedman2018-02-063-18/+61
| | | | | | | | | | | | | | | | | See D42509 for the original version of this. Basically, there are two significant changes to behavior here: - addLiveOuts always adds all pristine registers (even if a block has no successors). - addLiveOuts and addLiveOutsNoPristines always add all callee-saved registers for return blocks (including conditional return blocks). I cleaned up the functions a bit to make it clear these properties hold. Differential Revision: https://reviews.llvm.org/D42655 llvm-svn: 324422
* [AArch64] Adjust the cost model for Exynos M3Evandro Menezes2018-02-061-4/+4
| | | | | | | Fix the modeling of long division and SIMD conversion from integer and horizontal minimum and maximum. llvm-svn: 324417
* Add SelectionDAGDumper support for strict FP nodesAndrew Kaylor2018-02-061-0/+20
| | | | | | Patch by Kevin P. Neal llvm-svn: 324416
* Add OrcJIT dependency for Kaleidoscope Chapter 9.Lang Hames2018-02-061-0/+1
| | | | | | | This should fix the error at http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-expensive/10421 llvm-svn: 324413
* Fix a crash when emitting DIEs for variable-length arraysAdrian Prantl2018-02-064-33/+149
| | | | | | | | | | | | | VLAs may refer to a previous DIE to express the DW_AT_count of their type. Clang generates an artificial "vla_expr" variable for this. If this DIE hasn't been created yet LLVM asserts. This patch fixes this by sorting the local variables so that dependencies come before they are needed. It also replaces the linear scan in DWARFFile with a std::map, which can be faster. Differential Revision: https://reviews.llvm.org/D42940 llvm-svn: 324412
* [ORC] Use explicit constructor calls to fix a builder error atLang Hames2018-02-061-3/+3
| | | | | | http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/17627 llvm-svn: 324411
* [ORC] Remove some unused lambda captures.Lang Hames2018-02-062-7/+7
| | | | llvm-svn: 324410
* [X86] Add test cases that exercise the BSR/BSF optimization combineCMov.Craig Topper2018-02-061-0/+121
| | | | | | | | | | | | combineCmov tries to remove compares against BSR/BSF if we can prove the input to the BSR/BSF are never zero. As far as I can tell most of the time codegenprepare despeculates ctlz/cttz and gives us a cttz_zero_undef/ctlz_zero_undef which don't use a cmov. So the only way I found to trigger this code is to show codegenprepare an illegal type which it won't despeculate. I think we should be turning ctlz/cttz into ctlz_zero_undef/cttz_zero_undef for these cases before we ever get to operation legalization where the cmov is created. But wanted to add these tests so we don't regress. llvm-svn: 324409
* [x86] add tests to show demanded bits shortcoming; NFCSanjay Patel2018-02-061-0/+42
| | | | llvm-svn: 324408
* [docs] Add out-of-date warnings to the BuildingAJIT tutorial text.Lang Hames2018-02-063-0/+15
| | | | | | The text will be updated once the ORC API churn dies down. llvm-svn: 324406
* [ORC] Start migrating ORC layers to use the new ORC Core.h APIs.Lang Hames2018-02-0630-433/+812
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In particular this patch switches RTDyldObjectLinkingLayer to use orc::SymbolResolver and threads the requried changse (ExecutionSession references and VModuleKeys) through the existing layer APIs. The purpose of the new resolver interface is to improve query performance and better support parallelism, both in JIT'd code and within the compiler itself. The most visibile change is switch of the <Layer>::addModule signatures from: Expected<Handle> addModule(std::shared_ptr<ModuleType> Mod, std::shared_ptr<JITSymbolResolver> Resolver) to: Expected<Handle> addModule(VModuleKey K, std::shared_ptr<ModuleType> Mod); Typical usage of addModule will now look like: auto K = ES.allocateVModuleKey(); Resolvers[K] = createSymbolResolver(...); Layer.addModule(K, std::move(Mod)); See the BuildingAJIT tutorial code for example usage. llvm-svn: 324405
* [AArch64] add test to show sub-optimal isel; NFCSanjay Patel2018-02-061-0/+17
| | | | llvm-svn: 324404
* [x86] add test to show missed BMI isel; NFCSanjay Patel2018-02-061-0/+15
| | | | llvm-svn: 324403
* [DSE] Upgrade uses of MemoryIntrinic::getAlignment() to new API. (NFC)Daniel Neilson2018-02-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change is part of step five in the series of changes to remove alignment argument from memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the DeadStoreElimination pass to cease using the old getAlignment() API of MemoryIntrinsic in favour of getting dest specific alignments through the new API. Steps: Step 1) Remove alignment parameter and create alignment parameter attributes for memcpy/memmove/memset. ( rL322965, rC322964, rL322963 ) Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing source and dest alignments. ( rL323597 ) Step 3) Update Clang to use the new IRBuilder API. ( rC323617 ) Step 4) Update Polly to use the new IRBuilder API. ( rL323618 ) Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API, and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment() and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278, rL324384, rL324395 ) Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the MemIntrinsicInst::[get|set]Alignment() methods. Reference http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html llvm-svn: 324402
* [TargetLowering] use local variable to reduce duplication; NFCISanjay Patel2018-02-061-52/+32
| | | | llvm-svn: 324401
* [TargetLowering] use local variables to reduce duplication; NFCISanjay Patel2018-02-061-6/+6
| | | | llvm-svn: 324397
* [InferAddressSpaces] Update uses of IRBuilder memory intrinsic creation to ↵Daniel Neilson2018-02-061-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | new API Summary: This change is part of step five in the series of changes to remove alignment argument from memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the InferAddressSpaces pass to cease using: 1) The old getAlignment() API of MemoryIntrinsic in favour of getting source & dest specific alignments through the new API. 2) The old IRBuilder CreateMemCpy/CreateMemMove single-alignment APIs in favour of the new API that allows setting source and destination alignments independently. Steps: Step 1) Remove alignment parameter and create alignment parameter attributes for memcpy/memmove/memset. ( rL322965, rC322964, rL322963 ) Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing source and dest alignments. ( rL323597 ) Step 3) Update Clang to use the new IRBuilder API. ( rC323617 ) Step 4) Update Polly to use the new IRBuilder API. ( rL323618 ) Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API, and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment() and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278, rL324384 ) Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the MemIntrinsicInst::[get|set]Alignment() methods. Reference http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html llvm-svn: 324395
* [DWARFv5] Emit .debug_line_str (in a non-DWO file).Paul Robinson2018-02-067-35/+150
| | | | | | | | This should enable the linker to do string-pooling of path names. Differential Revision: https://reviews.llvm.org/D42707 llvm-svn: 324393
* [Hexagon] Extract HVX lowering and selection into HVX-specific files, NFCKrzysztof Parzyszek2018-02-066-581/+572
| | | | llvm-svn: 324392
* [Hexagon] Lower concat of more than 2 vectors into build_vectorKrzysztof Parzyszek2018-02-063-15/+59
| | | | llvm-svn: 324391
* [SLP] Update test checks, NFC.Alexey Bataev2018-02-063-64/+1127
| | | | llvm-svn: 324387
* [InlineFunction] Update deprecated use of IRBuilder CreateMemCpy (NFC)Daniel Neilson2018-02-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change is part of step five in the series of changes to remove alignment argument from memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the InlineFunction pass to ceause using the old IRBuilder CreateMemCpy single-alignment API in favour of the new API that allows setting source and destination alignments independently. Steps: Step 1) Remove alignment parameter and create alignment parameter attributes for memcpy/memmove/memset. ( rL322965, rC322964, rL322963 ) Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing source and dest alignments. ( rL323597 ) Step 3) Update Clang to use the new IRBuilder API. ( rC323617 ) Step 4) Update Polly to use the new IRBuilder API. ( rL323618 ) Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API, and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment() and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278 ) Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the MemIntrinsicInst::[get|set]Alignment() methods. Reference http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html llvm-svn: 324384
* [AMDGPU] removed dead code handling rmw in memory legalizerStanislav Mekhanoshin2018-02-061-66/+3
| | | | | | | | | It was always using cmpxchg path and in rmw and cmpxchg instructions are not distinguishable in the BE. Differential Revision: https://reviews.llvm.org/D42976 llvm-svn: 324383
* [Hexagon] Don't form new-value jumps from floating-point instructionsKrzysztof Parzyszek2018-02-062-0/+35
| | | | | | | Additionally, verify that the register defined by the producer is a 32-bit register. llvm-svn: 324381
* [InstCombine][ValueTracking] Match non-uniform constant power-of-two vectorsSimon Pilgrim2018-02-063-11/+33
| | | | | | | | Generalize existing constant matching to work with non-uniform constant vectors as well. Differential Revision: https://reviews.llvm.org/D42818 llvm-svn: 324369
* [X86] Auto-generate checks. NFCCraig Topper2018-02-061-102/+121
| | | | llvm-svn: 324367
* [ARM] f16 conversionsSjoerd Meijer2018-02-062-16/+68
| | | | | | | | | This is a follow up of r324321, adding f16 <-> f32 and f16 <-> f64 conversion match patterns. Differential Revision: https://reviews.llvm.org/D42954 llvm-svn: 324360
* [DAG, X86] Improve Dependency analysis when doing multi-nodeNirav Dave2018-02-0618-985/+645
| | | | | | | | | | | | | | | | | | | | Instruction Selection Cleanup cycle/validity checks in ISel (IsLegalToFold, HandleMergeInputChains) and X86 (isFusableLoadOpStore). Now do a full search for cycles / dependencies pruning the search when topological property of NodeId allows. As part of this propogate the NodeId-based cutoffs to narrow hasPreprocessorHelper searches. Reviewers: craig.topper, bogner Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D41293 llvm-svn: 324359
* Regenerate vector-urem test. NFCI.Simon Pilgrim2018-02-061-2/+2
| | | | llvm-svn: 324357
* AMDGPU: Fix S_BUFFER_LOAD_DWORD_SGPR moveToVALUMarek Olsak2018-02-062-2/+42
| | | | | | | | Author: Bas Nieuwenhuizen https://reviews.llvm.org/D42881 llvm-svn: 324353
* [Hexagon] Remove leftover assertKrzysztof Parzyszek2018-02-061-3/+1
| | | | llvm-svn: 324352
* [Hexagon] Split HVX operations on vector pairsKrzysztof Parzyszek2018-02-067-70/+342
| | | | | | | | Vector pairs are legal types, but not every operation can work on pairs. For those operations that are legal for single vectors, generate a concat of their results on pair halves. llvm-svn: 324350
* [Hexagon] Add helper functions to identify single/pair vector types, NFCKrzysztof Parzyszek2018-02-062-3/+17
| | | | llvm-svn: 324349
* [Hexagon] Handle lowering of SETCC via setCondCodeActionKrzysztof Parzyszek2018-02-066-132/+112
| | | | | | | | | | It was expanded directly into instructions earlier. That was to avoid loads from a constant pool for a vector negation: "xor x, splat(i1 -1)". Implement ISD opcodes QTRUE and QFALSE to denote logical vectors of all true and all false values, and handle setcc with negations through selection patterns. llvm-svn: 324348
* [X86][SSE] Add PACKUS support for truncation of clamped valuesSimon Pilgrim2018-02-062-51/+20
| | | | | | Followup to D42544 that matches PACKUSWB cases for non-AVX512, SSE and PACKUSDW cases will have to wait until we can add support for general SMIN/SMAX matching. llvm-svn: 324347
* [AMDGPU] do not generate .AMDGPU.config for amdpal os typeTim Renouf2018-02-062-18/+14
| | | | | | | | | | | | | | | Summary: Now we generate PAL metadata for the amdpal os type, there is no need to generate the .AMDGPU.config section. Reviewers: arsenm, nhaehnle, dstuttard Subscribers: kzhuravl, wdng, yaxunl, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D37760 Change-Id: I303c5fad66656ce97293da60621afac6595b4c18 llvm-svn: 324346
* [AArch64][SVE] Asm: Add AND_ZI instructions and aliasesSander de Smalen2018-02-066-0/+244
| | | | | | | | | | | | | | Summary: Adds support for the SVE AND instruction with vector and logical-immediate operands, and their corresponding aliases. Reviewers: fhahn, rengolin, samparker, echristo, aadg, kristof.beyls Reviewed By: fhahn Subscribers: aemerson, javed.absar, tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D42295 llvm-svn: 324343
* [MergeICmps] Handle chains with several complex BCE basic blocks.Clement Courbet2018-02-062-3/+62
| | | | | | | | | | - Fix condition for detecting that a complex basic block was the first in the chain. - Add tests. This was caught by buildbots when submitting rL324319. llvm-svn: 324341
* [X86][SSE] Add PACKSS support for truncation of clamped valuesSimon Pilgrim2018-02-062-49/+15
| | | | | | Followup to D42544 that matches PACKSSWB cases for non-AVX512, SSE and PACKSSDW cases will have to wait until we can add support for general SMIN/SMAX matching. llvm-svn: 324339
* [PowerPC] fix up in rL324229, NFCHiroshi Inoue2018-02-061-1/+1
| | | | | | This patch fixes up my previous commit (add initialization of local variables). llvm-svn: 324336
* [DeadArgumentElim] Set pointer to DISubprogram before calling RAUW. NFCPetar Jovanovic2018-02-061-3/+3
| | | | | | | | | | | | It is better to update pointer of the DISuprogram before we call RAUW for still live arguments of the function, because with the change reviewed in D42541 in RAUW we compare DISubprograms rather than functions itself. Patch by Djordje Todorovic. Differential Revision: https://reviews.llvm.org/D42794 llvm-svn: 324335
* Fix unused variable warning in release mode. NFC.Alexander Ivchenko2018-02-061-0/+1
| | | | llvm-svn: 324330
* [AArch64] Fix spelling of ICH_ELRSR_EL2 system registerOliver Stannard2018-02-063-4/+4
| | | | | | | This register was mis-spelled as ICH_ELSR_EL2, but has the correct encoding for ICH_ELRSR_EL2. llvm-svn: 324325
* [ARM][AArch64] Add CSDB speculation barrier instructionOliver Stannard2018-02-0610-11/+48
| | | | | | | | | | | | | | | This adds the CSDB instruction, which is a new barrier instruction described by the whitepaper at [1]. This is in encoding space which was previously executed as a NOP, so it is available for all targets that have the relevant NOP encoding space. This matches the binutils behaviour for these instructions [2][3]. [1] https://developer.arm.com/support/security-update [2] https://sourceware.org/ml/binutils/2018-01/msg00116.html [3] https://sourceware.org/ml/binutils/2018-01/msg00120.html llvm-svn: 324324
* [MergeICmps][NFC] Add more assertions.Clement Courbet2018-02-061-0/+4
| | | | llvm-svn: 324323
* [ARM] Armv8.2-A FP16 code generation (part 3/3)Sjoerd Meijer2018-02-064-42/+673
| | | | | | | | | | | | | | | This adds most of the FP16 codegen support, but these areas need further work: - FP16 literals and immediates are not properly supported yet (e.g. literal pool needs work), - Instructions that are generated from intrinsics (e.g. vabs) haven't been added. This will be addressed in follow-up patches. Differential Revision: https://reviews.llvm.org/D42849 llvm-svn: 324321
* Revert "[MergeICmps] Enable the MergeICmps Pass by default."Clement Courbet2018-02-064-20/+46
| | | | | | | | Breaks clang-ppc64be-linux-multistage buildbot. This reverts commit 515bab711f308c2e8299c49dd8c84ea6a2e0b60e. llvm-svn: 324319
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