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* Treat lifetime.start'd memory like we treat freshly alloca'd memory. Patch ↵Nick Lewycky2014-03-262-4/+37
| | | | | | by Björn Steinbrink! llvm-svn: 204876
* Reorder arguments on test command line to make it easier to cut andEric Christopher2014-03-261-1/+1
| | | | | | paste. llvm-svn: 204875
* [PowerPC] Generate VSX permutations for v2[fi]64 vectorsHal Finkel2014-03-264-5/+110
| | | | llvm-svn: 204873
* llvm-cov: Move XFAIL after the body of the testJustin Bogner2014-03-261-2/+3
| | | | | | | llvm-cov tests are sensitive to line number changes, so putting this at the end will limit churn when we fix the XFAIL. llvm-svn: 204871
* llvm-cov: Disable test on big endian machinesJustin Bogner2014-03-261-0/+2
| | | | llvm-svn: 204868
* CloneFunction: Clone all attributes, including the CCReid Kleckner2014-03-262-14/+39
| | | | | | | | | | | | | | | | Summary: Tested with a unit test because we don't appear to have any transforms that use this other than ASan, I think. Fixes PR17935. Reviewers: nicholas CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D3194 llvm-svn: 204866
* This is a fix for PR# 19051. I noticed code gen differences due to code ↵Ekaterina Romanova2014-03-262-1/+110
| | | | | | motion when running tests with and without the debug info at O2. The problem is in branch folding. A loop wanted to skip the debug info, but actually it didn't do so. llvm-svn: 204865
* Add comments. Addressing review comments from Evan on r204690.Manman Ren2014-03-261-0/+5
| | | | llvm-svn: 204864
* llvm-cov: Handle functions with no line numberJustin Bogner2014-03-265-1/+35
| | | | | | | | | Functions may in an instrumented binary but not in the original source when they're inserted by the compiler or the runtime. These functions aren't meaningful to the user, so teach llvm-cov to skip over them instead of crashing. llvm-svn: 204863
* Fix a problem with the ARM assembler incorrectly matching aKevin Enderby2014-03-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | vector list parameter that is using all lanes "{d0[], d2[]}" but can match and instruction with a ”{d0, d2}" parameter. I’m finishing up a fix for proper checking of the unsupported alignments on vld/vst instructions and ran into this. Thus I don’t have a test case at this time. And adding all code that will demonstrate the bug would obscure the very simple one line fix. So if you would indulge me on not having a test case at this time I’ll instead offer up a detailed explanation of what is going on in this commit message. This instruction: vld2.8 {d0[], d2[]}, [r4:64] is not legal as the alignment can only be 16 when the size is 8. Per this documentation: A8.8.325 VLD2 (single 2-element structure to all lanes) <align> The alignment. It can be one of: 16 2-byte alignment, available only if <size> is 8, encoded as a = 1. 32 4-byte alignment, available only if <size> is 16, encoded as a = 1. 64 8-byte alignment, available only if <size> is 32, encoded as a = 1. omitted Standard alignment, see Unaligned data access on page A3-108. So when code is added to the llvm integrated assembler to not match that instruction because of the alignment it then goes on to try to match other instructions and comes across this: vld2.8 {d0, d2}, [r4:64] and and matches it. This is because of the method ARMOperand::isVecListDPairSpaced() is missing the check of the Kind. In this case the Kind is k_VectorListAllLanes . While the name of the method may suggest that this is OK it really should check that the Kind is k_VectorList. As the method ARMOperand::isDoubleSpacedVectorAllLanes() is what was used to match {d0[], d2[]} and correctly checks the Kind: bool isDoubleSpacedVectorAllLanes() const { return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; } where the original ARMOperand::isVecListDPairSpaced() does not check the Kind: bool isVecListDPairSpaced() const { if (isSingleSpacedVectorList()) return false; return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] .contains(VectorList.RegNum)); } Jim Grosbach has reviewed the change and said: Yep, that sounds right. … And by "right" I mean, "wow, that's a nasty latent bug I'm really, really glad to see fixed." :) rdar://16436683 llvm-svn: 204861
* Add a unit test for Invoke iteration, similar to the one for CallEli Bendersky2014-03-261-11/+40
| | | | | | The tests are refactored to use the same fixture. llvm-svn: 204860
* PR15967 Fix in basicaa for faulty returning no alias.Arnold Schwaighofer2014-03-262-11/+74
| | | | | | | | | | | | | | This commit consist of two parts. The first part fix the PR15967. The wrong conclusion was made when the MaxLookup limit was reached. The fix introduce a out parameter (MaxLookupReached) to DecomposeGEPExpression that the function aliasGEP can act upon. The second part is introducing the constant MaxLookupSearchDepth to make sure that DecomposeGEPExpression and GetUnderlyingObject use the same search depth. This is a small cleanup to clarify the original algorithm. Patch by Karl-Johan Karlsson! llvm-svn: 204859
* Simplify PBQP graph removeAdjEdgeId implementation.Lang Hames2014-03-261-12/+10
| | | | llvm-svn: 204857
* Fix bot breakage in InstructionsTest.Eli Bendersky2014-03-261-1/+1
| | | | | | Makes sure the Call dies before the Function llvm-svn: 204856
* Fix problem with r204836Eli Bendersky2014-03-262-4/+32
| | | | | | | | | | In CallInst, op_end() points at the callee, which we don't want to iterate over when just iterating over arguments. Now take this into account when returning a iterator_range from arg_operands. Similar reasoning for InvokeInst. Also adds a unit test to verify this actually works as expected. llvm-svn: 204851
* [PowerPC] VSX loads and stores support unaligned accessHal Finkel2014-03-263-3/+28
| | | | | | | I've not yet updated PPCTTI because I'm not sure what the actual relative cost is compared to the aligned uses. llvm-svn: 204848
* Fix the ARM VST4 (single 4-element structure from one lane)Kevin Enderby2014-03-262-2/+2
| | | | | | | | | | | | | | | size 16 double-spaced registers instruction printing. This: vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]! was being printed as: vld4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]! rdar://16435096 llvm-svn: 204847
* Remove PBQP-cost dimension sanity assertion in PBQP::Graph::addConstructedEdge.Lang Hames2014-03-261-7/+0
| | | | | | We're already effectively checking sanity for that in PBQP::Graph::addEdge. llvm-svn: 204844
* [PowerPC] Use v2f64 <-> v2i64 VSX conversion instructionsHal Finkel2014-03-263-4/+85
| | | | llvm-svn: 204843
* Change the PBQP graph adjacency list structure from std::set to std::vector.Lang Hames2014-03-261-21/+105
| | | | | | | | | | | | | | The edge data structure (EdgeEntry) now holds the indices of its entries in the adjacency lists of the nodes it connects. This trades a little ugliness for faster insertion/removal, which is now O(1) with a cheap constant factor. All of this is implementation detail within the PBQP graph, the external API remains unchanged. Individual register allocations are likely to change, since the adjacency lists will now be ordered differently (or rather, will now be unordered). This shouldn't affect the average quality of allocations however. llvm-svn: 204841
* R600: Add a testcase for sext_in_reg I missed.Matt Arsenault2014-03-262-0/+16
| | | | | | This sext_inreg i32 in i64 case was already handled, but not enabled. llvm-svn: 204840
* [PowerPC] Remove some dead VSX v4f32 store patternsHal Finkel2014-03-261-4/+2
| | | | | | | | | These patterns are dead (because v4f32 stores are currently promoted to v4i32 and stored using Altivec instructions), and also are likely not correct (because they'd store the vector elements in the opposite order from that assumed by the rest of the Altivec code). llvm-svn: 204839
* [PowerPC] Use VSX vector load/stores for v2[fi]64Hal Finkel2014-03-263-0/+49
| | | | | | | | These instructions have access to the complete VSX register file. In addition, they "swap" the order of the elements so that element 0 (the scalar part) comes first in memory and element 1 follows at a higher address. llvm-svn: 204838
* [MCJIT] Check if there have been errors during RuntimeDyld execution.Juergen Ributzka2014-03-263-1/+4
| | | | llvm-svn: 204837
* Enable range-for iteration over call/invoke arguments.Eli Bendersky2014-03-261-1/+22
| | | | | | Similar to r204835 llvm-svn: 204836
* Add args() iteartor adapter to Function, for range-for loops.Eli Bendersky2014-03-261-3/+14
| | | | | | | | | | | This patch is in similar vein to what done earlier to Module::globals/aliases etc. It allows to iterate over function arguments like this: for (Argument Arg : F.args()) { ... } llvm-svn: 204835
* Fix for incorrect address sinking in the presence of potential overflows.Jim Grosbach2014-03-262-1/+34
| | | | | | | | | | | | | In some cases it is possible for CGP to attempt to reuse a base address from another basic block. In those cases we have to be sure that all the address math was either done at the same bit width, or that none of it overflowed before it was extended. Patch by Louis Gerbarg <lgg@apple.com> rdar://16307442 llvm-svn: 204833
* Revert "X86 memcpy lowering: use "rep movs" even when esi is used as base ↵Hans Wennborg2014-03-263-39/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | pointer" (r204174) > For functions where esi is used as base pointer, we would previously fall ba > from lowering memcpy with "rep movs" because that clobbers esi. > > With this patch, we just store esi in another physical register, and restore > it afterwards. This adds a little bit of register preassure, but the more > efficient memcpy should be worth it. > > Differential Revision: http://llvm-reviews.chandlerc.com/D2968 This didn't work. I was ending up with code like this: lea edi,[esi+38h] mov ecx,0Fh mov edx,esi mov esi,ebx rep movs dword ptr es:[edi],dword ptr [esi] lea ecx,[esi+74h] <-- Ooops, we're now using esi before restoring it from edx. add ebx,3Ch mov esi,edx I guess if we want to do this we need stronger glue or something, or doing the expansion much later. llvm-svn: 204829
* [PowerPC] Add v2i64 as a legal VSX typeHal Finkel2014-03-265-10/+54
| | | | | | | | | v2i64 needs to be a legal VSX type because it is the SetCC result type from v2f64 comparisons. We need to expand all non-arithmetic v2i64 operations. This fixes the lowering for v2f64 VSELECT. llvm-svn: 204828
* [mips] Use TwoOperandAliasConstraint for ArithLogicR instructions.Matheus Almeida2014-03-265-24/+17
| | | | | | | | This enables TableGen to generate an additional two operand matcher for our ArithLogicR class of instructions (constituted by 3 register operands). E.g.: and $1, $2 <=> and $1, $1, $2 llvm-svn: 204826
* [mips] Add support to the '.dword' directive.Matheus Almeida2014-03-262-0/+41
| | | | | | | The '.dword' directive accepts a list of expressions and emits them in 8-byte chunks in successive locations. llvm-svn: 204822
* Clarify that select is only non-branching on the IR-level, it often endsJoerg Sonnenberger2014-03-261-1/+1
| | | | | | up as jump table or other forms of branches on the machine level. llvm-svn: 204819
* [mips] Rename function in MipsAsmParser.Matheus Almeida2014-03-261-4/+4
| | | | | | | | | | | | parseDirectiveWord is a generic function that parses an expression which means there's no need for it to have such an specific name. Renaming it to parseDataDirective so that it can also be used to handle .dword directives[1]. [1]To be added in a follow up commit. No functional changes. llvm-svn: 204818
* [mips] Add support to '.set mips64'.Matheus Almeida2014-03-264-0/+22
| | | | | | | | | | The '.set mips64' directive enables the feature Mips:FeatureMips64 from assembly. Note that it doesn't modify the ELF header as opposed to the use of -mips64 from the command-line. The reason for this is that we want to be as compatible as possible with existing assemblers like GAS. llvm-svn: 204817
* AArch64_BE Elf support for MC-JIT runtime dynamic linkerChristian Pirker2014-03-264-2/+5
| | | | llvm-svn: 204816
* [mips] Add support to '.set mips64r2'.Matheus Almeida2014-03-264-0/+22
| | | | | | | | | | The '.set mips64r2' directive enables the feature Mips:FeatureMips64r2 from assembly. Note that it doesn't modify the ELF header as opposed to the use of -mips64r2 from the command-line. The reason for this is that we want to be as compatible as possible with existing assemblers like GAS. llvm-svn: 204815
* AArch64_BE function argument passing for ARM ABIChristian Pirker2014-03-265-20/+56
| | | | llvm-svn: 204814
* ARM: add intrinsics for the v8 ldaex/stlexTim Northover2014-03-266-26/+194
| | | | | | | | | We've already got versions without the barriers, so this just adds IR-level support for generating the new v8 ones. rdar://problem/16227836 llvm-svn: 204813
* Clarify llvm.clear_cache description.Joerg Sonnenberger2014-03-261-20/+13
| | | | llvm-svn: 204812
* [mips] Hoist common functionality into a new function.Matheus Almeida2014-03-261-29/+30
| | | | | | | | | | Given that we support multiple directives that enable a particular feature (e.g. '.set mips16'), it's best to hoist that code into a new function so that we don't repeat the same pattern w.r.t parsing and handling error cases. No functional changes. llvm-svn: 204811
* Change @llvm.clear_cache default to call rt-libRenato Golin2014-03-264-15/+16
| | | | | | | | | | | After some discussion on IRC, emitting a call to the library function seems like a better default, since it will move from a compiler internal error to a linker error, that the user can work around until LLVM is fixed. I'm also adding a note on the responsibility of the user to confirm that the cache was cleared on platforms where nothing is done. llvm-svn: 204806
* [mips] The decision to use MO_GOT_PAGE and MO_GOT_OFST depends on the ABI ↵Daniel Sanders2014-03-262-9/+11
| | | | | | | | | | | | | | being N32 or N64 not the arch being MIPS64 Summary: No functional change (in supported use cases) Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3177 llvm-svn: 204805
* Fix AVX512 Gather and Scatter execution domains.Cameron McInally2014-03-262-7/+94
| | | | llvm-svn: 204804
* [mips] Add support for '.option pic2'.Matheus Almeida2014-03-265-0/+52
| | | | | | | | | The directive '.option pic2' enables PIC from assembly source. At the moment none of the macros/directives check the PIC bit but that's going to be fixed relatively soon. For example, the expansion of macros like 'la' depend on the relocation model. llvm-svn: 204803
* Add @llvm.clear_cache builtinRenato Golin2014-03-2610-0/+135
| | | | | | | | | | | | | | | | | Implementing the LLVM part of the call to __builtin___clear_cache which translates into an intrinsic @llvm.clear_cache and is lowered by each target, either to a call to __clear_cache or nothing at all incase the caches are unified. Updating LangRef and adding some tests for the implemented architectures. Other archs will have to implement the method in case this builtin has to be compiled for it, since the default behaviour is to bail unimplemented. A Clang patch is required for the builtin to be lowered into the llvm intrinsic. This will be done next. llvm-svn: 204802
* [PowerPC] Lower VSELECT using xxsel when VSX is availableHal Finkel2014-03-263-3/+99
| | | | | | | | With VSX there is a real vector select instruction, and so we should use it. Note that VSELECT will still scalarize for v2f64 because the corresponding SetCC result type (v2i64) is not currently a legal type. llvm-svn: 204801
* [mips] Add tests for t0-t3 for N32/N64Daniel Sanders2014-03-261-33/+40
| | | | | | | These are aliases of t4-t7 and are provided for compatibility with both the original ABI documentation (using t4-t7) and GNU As (using t0-t3) llvm-svn: 204797
* [mips] The register names depend on the ABI being N32/N64 rather than the ↵Daniel Sanders2014-03-264-16/+64
| | | | | | | | | | | | | | arch being mips64 Summary: Added test cases for O32 and N32 on MIPS64. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3175 llvm-svn: 204796
* Follow-up to r204790: don't try to emit line tables if there are no ↵Timur Iskhodzhanov2014-03-262-2/+61
| | | | | | functions with DI in the TU llvm-svn: 204795
* [mips] $s8 is an alias for $fp in all ABI's, not just N32/N64.Daniel Sanders2014-03-263-3/+4
| | | | llvm-svn: 204793
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