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* R600/SI: Expand ashr of v2i32/v4i32 for SIAaron Watry2013-06-252-7/+36
| | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184842
* R600/SI: Expand srl of v2i32/v4i32 for SIAaron Watry2013-06-252-7/+37
| | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184841
* R600/SI: Expand shl of v2i32/v4i32 for SIAaron Watry2013-06-252-7/+37
| | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184840
* R600/SI: Expand or of v2i32/v4i32 for SIAaron Watry2013-06-252-7/+37
| | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184839
* R600/SI: Expand mul of v2i32/v4i32 for SIAaron Watry2013-06-252-6/+35
| | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184838
* R600/SI: Expand and of v2i32/v4i32 for SIAaron Watry2013-06-252-6/+34
| | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184837
* BlockFrequency: Bump up the entry frequency a bit.Benjamin Kramer2013-06-256-32/+22
| | | | | | | This is a band-aid to fix the most severe regressions we're seeing from basing spill decisions on block frequencies, until we have a better solution. llvm-svn: 184835
* [PowerPC] Add extended rotate/shift mnemonicsUlrich Weigand2013-06-253-52/+349
| | | | | | This adds all missing extended rotate/shift mnemonics to the asm parser. llvm-svn: 184834
* [PowerPC] Add rldcr/rldic instructionsUlrich Weigand2013-06-252-4/+16
| | | | | | | | This adds pattern for the rldcr and rldic instructions (the last instruction from the rotate/shift family that were missing). They are currently used only by the asm parser. llvm-svn: 184833
* [PowerPC] Add extended subtract mnemonicsUlrich Weigand2013-06-253-1/+73
| | | | | | | | | | | | | | | This adds support for the extended subtract mnemonics to the asm parser: subi subis subic subic. sub sub. subc subc. llvm-svn: 184832
* [NVPTX] Default pointer type doesn't make sense for getParamSymbol()Justin Holewinski2013-06-252-2/+2
| | | | llvm-svn: 184831
* Fix a typo in the code that collected the costs recursively.Nadav Rotem2013-06-251-1/+1
| | | | llvm-svn: 184827
* keep only the StringRef version of getFileOrSTDIN.Rafael Espindola2013-06-259-22/+10
| | | | llvm-svn: 184826
* Don't assume ResultPath is null terminated.Rafael Espindola2013-06-251-1/+2
| | | | llvm-svn: 184824
* Revert "Temporarily enable MI-Sched on X86."Andrew Trick2013-06-2564-277/+258
| | | | | | This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c. llvm-svn: 184823
* R600/SI: Report unaligned memory accesses as legal for > 32-bit typesTom Stellard2013-06-253-0/+45
| | | | | | | | | | | In reality, some unaligned memory accesses are legal for 32-bit types and smaller too, but it all depends on the address space. Allowing unaligned loads/stores for > 32-bit types is mainly to prevent the legalizer from splitting one load into multiple loads of smaller types. https://bugs.freedesktop.org/show_bug.cgi?id=65873 llvm-svn: 184822
* R600: Add support for i32 loads from the constant address space on CaymanTom Stellard2013-06-252-0/+10
| | | | | Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 184821
* R600/SI: Add support for v4i32 and v4f32 kernel argsTom Stellard2013-06-252-10/+15
| | | | | Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 184820
* R600: Fix typo in R600Schedule.tdTom Stellard2013-06-252-2/+36
| | | | | | | | | | | | | | | | This should only make a difference in programs that use a lot of the vector ALU instructions like BFI_INT and BIT_ALIGN. There is a slight improvement in the phatk bitcoin mining kernel with this patch on Evergreen (vector size == 1): Before: 1173 Instruction Groups / 9520 dwords After: 1167 Instruction Groups / 9510 dwords Reviewed-by: Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 184819
* PPCAsmParser.cpp: Quote "@l/@ha" in comments. [-Wdocumentation]NAKAMURA Takumi2013-06-251-2/+2
| | | | llvm-svn: 184809
* Add an autoconf option for turning on -gsplit-dwarf by defaultEric Christopher2013-06-254-4/+47
| | | | | | | | | | | | | when building llvm. This saves quite a bit of time and space when linking. Please report any problems via bugzilla. Caveats: a) This will only work on linux b) This requires a fairly new binutils c) This requires a fairly new gdb llvm-svn: 184808
* Create a replacement for sys::Path::PathSeparator.Rafael Espindola2013-06-251-0/+9
| | | | llvm-svn: 184806
* Cleanup in unique_file when we only want the name.Rafael Espindola2013-06-251-2/+10
| | | | | | | | | This is really ugly, but it is no worse than what we have in clang right now and it is better to get it working first and clean/optimize it afterwards. Will be tested from clang in the next patch. llvm-svn: 184802
* As far as I know no linker needs or wants the -g flag.Eric Christopher2013-06-251-4/+1
| | | | llvm-svn: 184800
* Remove all non-linker oriented compile options from the linkerEric Christopher2013-06-241-4/+3
| | | | | | | | | | | command line. Change the darwin universal binary options to be TargetCommonOpts so that they'll be passed to the linker since -arch at least is still needed. Someone on darwin with a buildit based build should probably verify that this doesn't break anything there. llvm-svn: 184793
* 80-column and tab character fixes.Eric Christopher2013-06-243-5/+8
| | | | llvm-svn: 184792
* Formatting.Eric Christopher2013-06-241-3/+2
| | | | llvm-svn: 184788
* typo.Adrian Prantl2013-06-241-1/+1
| | | | llvm-svn: 184783
* Use const references instead of pointers to references that areEric Christopher2013-06-242-21/+23
| | | | | | never modified. No functional change. llvm-svn: 184781
* [PowerPC] Support some miscellaneous mnemonics in the asm parserUlrich Weigand2013-06-243-5/+27
| | | | | | | | | | | This adds support for the following extended mnemonics: xnop mr. not not. la llvm-svn: 184767
* Add a simpler version of is_regular_file.Rafael Espindola2013-06-241-0/+9
| | | | llvm-svn: 184764
* DebugInfo: DIBuilder changes to match DIEnumerator changes in r184694David Blaikie2013-06-242-2/+2
| | | | | | | | Representing enumerators by int64 instead of uint64 for now. At some point we need to address the underlying issue of representation depending on the specific enumeration. llvm-svn: 184761
* Improve diagnostics when getSizeInBits is called on the Other type.Chad Rosier2013-06-241-2/+4
| | | | llvm-svn: 184760
* PPC: Remove default case from fully covered switch.Benjamin Kramer2013-06-241-4/+2
| | | | llvm-svn: 184758
* [PowerPC] Add some FIXMEsUlrich Weigand2013-06-241-0/+25
| | | | | | | A bunch of extendend mnemomics ought to support '.' forms. Add FIXMEs to the test case for those. llvm-svn: 184757
* R600: Fix spelling error in commentAaron Watry2013-06-241-1/+1
| | | | | | our -> or llvm-svn: 184756
* [PowerPC] Add predicted forms of branchesUlrich Weigand2013-06-247-68/+1395
| | | | | | | | | | | | | | | | | | | | This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
* Move llvm/test/DebugInfo/arguments.ll to X86, for now. It is still Windows' ↵NAKAMURA Takumi2013-06-241-0/+0
| | | | | | PECOFF incompatible. llvm-svn: 184750
* Rename the variable to fix a warning. Thanks Andy Gibbs.Nadav Rotem2013-06-241-2/+2
| | | | llvm-svn: 184749
* Look for Python 2 before Python 3 in CMakeLists.txtReid Kleckner2013-06-241-1/+2
| | | | | | | | | All of LLVM's Python scripts only support Python 2 for widely understood reasons. Patch by Yonggang Luo. llvm-svn: 184732
* llvm/test/CodeGen/X86: Add explicit -mtriple=x86_64-unknown-unknown.NAKAMURA Takumi2013-06-242-2/+2
| | | | llvm-svn: 184731
* llvm/test/CodeGen/X86/legalize-shift-64.ll: Add explicit ↵NAKAMURA Takumi2013-06-241-1/+1
| | | | | | -mtriple=i686-unknown-unknown. llvm-svn: 184730
* llvm/test/DebugInfo/arguments.ll: Add explicit -mtriple=x86_64-unknown-unknown.NAKAMURA Takumi2013-06-241-1/+1
| | | | llvm-svn: 184729
* NVPTXTargetObjectFile.h: Initialize some pointers as NULL in the constructor ↵NAKAMURA Takumi2013-06-241-1/+23
| | | | | | | | of NVPTXTargetObjectFile. ~NVPTXTargetObjectFile() tries to delete them. It caused crash on some hosts since r184595. llvm-svn: 184728
* [PowerPC] Add t/f branch mnemonics to asm parserUlrich Weigand2013-06-242-81/+127
| | | | | | | This adds the bt/bf/bd(n)zt/bd(n)zf mnemonics as aliases for the asm parser, resolving to the generic conditional patterns. llvm-svn: 184725
* Reapply 184685 after the SetVector iteration order fix.Arnold Schwaighofer2013-06-244-234/+328
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This should hopefully have fixed the stage2/stage3 miscompare on the dragonegg testers. "LoopVectorize: Use the dependence test utility class We now no longer need alias analysis - the cases that alias analysis would handle are now handled as accesses with a large dependence distance. We can now vectorize loops with simple constant dependence distances. for (i = 8; i < 256; ++i) { a[i] = a[i+4] * a[i+8]; } for (i = 8; i < 256; ++i) { a[i] = a[i-4] * a[i-8]; } We would be able to vectorize about 200 more loops (in many cases the cost model instructs us no to) in the test suite now. Results on x86-64 are a wash. I have seen one degradation in ammp. Interestingly, the function in which we now vectorize a loop is never executed so we probably see some instruction cache effects. There is a 2% improvement in h264ref. There is one or the other TSCV loop kernel that speeds up. radar://13681598" llvm-svn: 184724
* LoopVectorize: Use SetVector for the access setArnold Schwaighofer2013-06-241-1/+2
| | | | | | | We are creating the runtime checks using this set so we need a deterministic iteration order. llvm-svn: 184723
* [PowerPC] Support generic conditional branches in asm parserUlrich Weigand2013-06-243-9/+84
| | | | | | | | | | | This adds instruction patterns to cover the generic forms of the conditional branch instructions. This allows the assembler to support the generic mnemonics. The compiler will still generate the various specific forms of the instruction that were already supported. llvm-svn: 184722
* [PowerPC] Support absolute branchesUlrich Weigand2013-06-2414-76/+344
| | | | | | | | | | | | | | | | | | There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
* [PowerPC] Support bd(n)zl and bd(n)zlrlUlrich Weigand2013-06-242-4/+22
| | | | | | | This adds support for the bd(n)zl and bd(n)zlrl instructions. The patterns are currently used for the asm parser only. llvm-svn: 184720
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