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* Rename test since it's not linux-specific.Bill Wendling2012-08-131-0/+0
| | | | llvm-svn: 161792
* ARM: enable struct byval for AAPCS-VFP.Manman Ren2012-08-131-0/+3
| | | | | | | | This change is to be enabled in clang. rdar://9877866 llvm-svn: 161789
* Whitespace cleanup.Bill Wendling2012-08-131-7/+7
| | | | llvm-svn: 161788
* Count triangles and diamonds in early if-conversion.Jakob Stoklund Olesen2012-08-131-0/+16
| | | | llvm-svn: 161783
* Delete dead typedef.Jakob Stoklund Olesen2012-08-131-2/+0
| | | | llvm-svn: 161782
* Handle extra Tail predecessors in if-conversion.Jakob Stoklund Olesen2012-08-132-20/+97
| | | | | | | | It is still possible to if-convert if the tail block has extra predecessors, but the tail phis must be rewritten instead of being removed. llvm-svn: 161781
* [Hexagon] Don't mark callee saved registers as clobbered by a tail callArnold Schwaighofer2012-08-132-9/+17
| | | | | | | | | | This was causing unnecessary spills/restores of callee saved registers. Fixes PR13572. Patch by Pranav Bhandarkar! llvm-svn: 161778
* Fix failure on Atom bot due to r161769Manman Ren2012-08-131-1/+1
| | | | llvm-svn: 161777
* Do not optimize (or (and X,Y), Z) into BFI and other sequences if the AND ↵Nadav Rotem2012-08-132-1/+22
| | | | | | | | ISDNode has more than one user. rdar://11876519 llvm-svn: 161775
* X86: move Int_CVTSD2SSrr, Int_CVTSI2SSrr, Int_CVTSI2SDrr, Int_CVTSS2SDrr fromManman Ren2012-08-132-6/+20
| | | | | | | | | OpTbl1 to OpTbl2 since they have 3 operands and the last operand can be changed to a memory operand. PR13576 llvm-svn: 161769
* Add support for the %H output modifier.Eric Christopher2012-08-132-2/+24
| | | | | | Patch by Weiming Zhao. llvm-svn: 161768
* X86: when auto-detecting the subtarget features, make sure use IsIntel to detectManman Ren2012-08-131-2/+2
| | | | | | Nehalem, Westmere and Sandy Bridge. AMD also has processor family 6. llvm-svn: 161763
* Fix a documentation typo.Nadav Rotem2012-08-131-2/+2
| | | | llvm-svn: 161758
* [asan] remove the code for --asan-merge-callbacks as it appears to be a bad ↵Kostya Serebryany2012-08-131-78/+8
| | | | | | idea. (partly related to Bug 13225) llvm-svn: 161757
* Added test for non-static use of cl::opt (fixed in r160170)Alexander Kornienko2012-08-131-0/+11
| | | | llvm-svn: 161751
* Add test for previous commit correcting NEON load patterns.Tim Northover2012-08-131-0/+102
| | | | llvm-svn: 161750
* Use correct loads for vector types during extending-load operations.Tim Northover2012-08-131-36/+36
| | | | | | | | Previously, we used VLD1.32 in all cases, however there are both 16 and 64-bit accesses being selected, so we need to use an appropriate width load in those cases. llvm-svn: 161748
* Tidy up VSETCC lowering code a bit more by adding an llvm_unreachable and ↵Craig Topper2012-08-131-7/+9
| | | | | | putting an a couple if conditions in a better order. llvm-svn: 161746
* Refactor code a bit to share commonalities. No functional change intended.Craig Topper2012-08-131-20/+21
| | | | llvm-svn: 161745
* Fix an unused variable warning from r161742.Craig Topper2012-08-131-3/+0
| | | | llvm-svn: 161743
* Remove the LowerMMXCONCAT_VECTORS function. It could never execute because ↵Craig Topper2012-08-133-57/+1
| | | | | | there are no legal 64-bit vector types that could be used as inputs to a 128-bit concat_vectors. Remove a target specific SDNode and its patterns that become unused as a result. llvm-svn: 161742
* Give this test an explicit triple.Nick Lewycky2012-08-121-1/+1
| | | | llvm-svn: 161740
* When emitting the PC range in an FDE, use the same data encoding for both endsNick Lewycky2012-08-122-9/+34
| | | | | | of the range. Fixes PR13581! llvm-svn: 161739
* Remove call to setOperationAction for SETCC of v4f32. SETCC returns an ↵Craig Topper2012-08-121-1/+0
| | | | | | integer type not an FP type. llvm-svn: 161738
* Remove unnecessary call to setOperationAction for SETCC of v2i64 under ↵Craig Topper2012-08-121-3/+0
| | | | | | SSE42. It was already called for the same under SSE2. llvm-svn: 161737
* Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARMArnold Schwaighofer2012-08-127-339/+17
| | | | | | | | | architecture It broke MultiSource/Applications/JM/ldecod/ldecod on armv7 thumb O0 g and armv7 thumb O3. llvm-svn: 161736
* Change addTypeForNeon to use MVT instead of EVT so all the calls to ↵Craig Topper2012-08-122-51/+46
| | | | | | getSimpleVT can be removed. llvm-svn: 161735
* Make replace many calls to getSizeInBits() with is128BitVector/is256BitVectorCraig Topper2012-08-121-60/+65
| | | | llvm-svn: 161734
* Use MVT.isXBitVector instead of EVT.isXBitVector when setting up operation ↵Craig Topper2012-08-121-41/+35
| | | | | | actions. Compiles to smaller code. llvm-svn: 161733
* fix PR13577, an issue introduced by r161687Michael Liao2012-08-112-1/+27
| | | | | | | | - FCMOV only supports a subset of X86 conditions. Skip boolean simplification if X86 condition is not valid for FCMOV. - add a minimal test case for PR13577. llvm-svn: 161732
* Create isXBitVector methods in MVT and call them from EVT. This allows ↵Craig Topper2012-08-111-19/+39
| | | | | | targets to call them with an MVT without needing to convert to EVT. llvm-svn: 161731
* Move setOperationAction for CONCAT_VECTORS for 256-bit vectors into loop ↵Craig Topper2012-08-111-7/+2
| | | | | | since all 256-bit types are supported. llvm-svn: 161730
* MachineCSE: Hoist isConstantPhysReg out of the loop, it checks for overlaps ↵Benjamin Kramer2012-08-111-4/+3
| | | | | | already. llvm-svn: 161729
* PR13578: Teach MachineCSE that instructions that use a constant register can ↵Benjamin Kramer2012-08-113-4/+29
| | | | | | | | be CSE'd safely. This is common e.g. when doing rip-relative addressing on x86_64. llvm-svn: 161728
* Tidy up indentation. No functional change.Craig Topper2012-08-111-25/+25
| | | | llvm-svn: 161727
* Fix a cast that was casting away 'const' unnecessarily Craig Topper2012-08-111-1/+1
| | | | llvm-svn: 161726
* Add a couple default: llvm_unreachable() to some switch statements. Fix a ↵Craig Topper2012-08-111-2/+4
| | | | | | bad message in an existing llvm_unreachable. llvm-svn: 161725
* X86: when we are auto-detecting the subtarget features, make sure we turn onManman Ren2012-08-102-3/+8
| | | | | | | | | | FeatureFastUAMem for Nehalem, Westmere and Sandy Bridge. FeatureFastUAMem is already on if we pass in nehalem or westmere as a command argument. rdar: 7252306 llvm-svn: 161717
* Add a proper if-conversion cost model.Jakob Stoklund Olesen2012-08-101-13/+77
| | | | | | | | | | | | | | Detect when there is not enough available ILP, so if-conversion can't speculate instructions for free. Compute the lengthening of the critical path when inserting a select instruction that depends on the condition as well as both sides of the if. Reject conversions that would stretch the critical path by more than half a mispredict penalty. llvm-svn: 161713
* Give MachineTraceMetrics its own debug tag.Jakob Stoklund Olesen2012-08-101-1/+1
| | | | llvm-svn: 161712
* Add more trace query functions.Jakob Stoklund Olesen2012-08-102-0/+42
| | | | | | | | | | | Trace::getResourceLength() computes the number of cycles required to execute the trace when ignoring data dependencies. The number can be compared to the critical path to estimate the trace ILP. Trace::getPHIDepth() computes the data dependency depth of a PHI in a trace successor that isn't necessarily part of the trace. llvm-svn: 161711
* The normal edge of an invoke is not allowed to branch to a block with aEli Friedman2012-08-109-1205/+25
| | | | | | landingpad. Enforce it in the verifier, and fix the regression tests to match. llvm-svn: 161697
* ARM: enable struct byval for AAPCS.Manman Ren2012-08-101-0/+3
| | | | | | | | | This change is to be enabled in clang. rdar://9877866 PR://13350 llvm-svn: 161693
* Add getTPred() and getFPred() functions.Jakob Stoklund Olesen2012-08-101-2/+8
| | | | | | They identify the PHI predecessors in both diamonds and triangles. llvm-svn: 161689
* Include loop-carried dependencies when computing instr heights.Jakob Stoklund Olesen2012-08-101-6/+18
| | | | | | | | | When a trace ends with a back-edge, include PHIs in the loop header in the height computations. This makes the critical path through a loop more accurate by including the latencies of the last instructions in the loop. llvm-svn: 161688
* add X86-specific DAG optimization to simplify boolean testMichael Liao2012-08-102-4/+155
| | | | | | | | | | | | | - if a boolean test (X86ISD::CMP or X86ISD:SUB) checks a boolean value generated from X86ISD::SETCC, try to simplify the boolean value generation and checking by reusing the original EFLAGS with proper condition code - add hooks to X86 specific SETCC/BRCOND/CMOV, the major 3 places consuming EFLAGS part of patches fixing PR12312 llvm-svn: 161687
* A couple of addition comment fixesEli Bendersky2012-08-101-2/+2
| | | | llvm-svn: 161678
* Fix a couple of typos in commentsEli Bendersky2012-08-101-2/+2
| | | | llvm-svn: 161677
* Constify some basic blocks, no functionality change.Rafael Espindola2012-08-101-8/+8
| | | | llvm-svn: 161668
* remove tailing whitespaces and test commitMichael Liao2012-08-101-3/+3
| | | | llvm-svn: 161664
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