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* Try to unbreak the windows build.Benjamin Kramer2012-07-201-1/+1
| | | | llvm-svn: 160567
* SourceMgr: Use has_colors() instead of just is_displayed() before trying to useDaniel Dunbar2012-07-201-2/+2
| | | | | | color. llvm-svn: 160559
* raw_ostream: Add a has_colors() method.Daniel Dunbar2012-07-202-0/+9
| | | | llvm-svn: 160558
* Process: Add sys::Process::FileDescriptorHasColors().Daniel Dunbar2012-07-203-10/+20
| | | | llvm-svn: 160557
* lit: Use close_fds=True on UNIX, to avoid file descriptor pollution ofDaniel Dunbar2012-07-201-1/+5
| | | | | | subprocesses. llvm-svn: 160556
* Fix assertion in jump threading (PR13405).Richard Osborne2012-07-202-0/+10
| | | | | | | | GetBestDestForJumpOnUndef() assumes there is at least 1 successor, which isn't true if the block ends in an indirect branch with no successors. Fix this by bailing out earlier in this case. llvm-svn: 160546
* [asan] make sure that the crash callbacks do not get merged (Chandler's ↵Kostya Serebryany2012-07-202-22/+35
| | | | | | idea: insert an empty InlineAsm). Change the order in which the new BBs are inserted: the slow path BB is insert between old BBs, the crash BB is inserted at the end. Don't create an empty BB (introduced by recent commits). Update the test. The experimental code that does manual crash callback merge will most likely be deleted later. llvm-svn: 160544
* Don't use implicit register operands to calculate L-bit for AVX ↵Craig Topper2012-07-201-0/+2
| | | | | | instructions. Needed because super reg defs and kills are added as implicit operands on 128-bit instructions. Fixes PR13349. Patch by Jose Fonseca. llvm-svn: 160543
* Make RegisterOperand a subclass of DAGOperand so that RegisterOperands can ↵Owen Anderson2012-07-201-1/+2
| | | | | | be passed into multiclasses that take DAGOperands as multiclass parameters. llvm-svn: 160540
* Revert r160529 due to crashes.Nick Lewycky2012-07-193-192/+9
| | | | llvm-svn: 160532
* Fix crash in machine verifier when trying to print the def of a register ↵Pete Cooper2012-07-191-0/+2
| | | | | | which has no def llvm-svn: 160531
* Don't wipe out global variables that are probably storing pointers to heapNick Lewycky2012-07-193-9/+192
| | | | | | memory. This makes clang play nice with leak checkers. llvm-svn: 160529
* Reverting r 160419.Galina Kistanova2012-07-191-2/+1
| | | | llvm-svn: 160525
* Adds the family codes for the Midview Atom processors so that thePreston Gurd2012-07-192-4/+3
| | | | | | Atom buildbot will auto-detect Atom. llvm-svn: 160521
* Fix remaining lit tests which were failing when run on an AtomPreston Gurd2012-07-1912-16/+51
| | | | | | | | processor. Patches by Tyler Nowicki, Andy Zhang, and Preston Gurd! llvm-svn: 160520
* default to use -mv4 when no version of Hexagon has been specifiedSebastian Pop2012-07-191-1/+5
| | | | | | | | | This fixes a bunch of make check failures of the form: Unknown Architecture Version. UNREACHABLE executed at ../lib/Target/Hexagon/HexagonSubtarget.cpp:60! llvm-svn: 160518
* reimplement truncate() to make it optimal.Nuno Lopes2012-07-191-10/+45
| | | | | | | | It is optimal at least up to 7 bits (I've tested all such cases) This change to truncate() allows a little simplification to the multiplication code, and it also makes multiplication optimal :) llvm-svn: 160512
* Pull the simple parts of DenseMapInfo<DebugLoc> inline and prune includes.Benjamin Kramer2012-07-192-17/+4
| | | | llvm-svn: 160507
* test/DebugInfo/dwarfdump-test.test: Tweak expressions for Win32 to match ↵NAKAMURA Takumi2012-07-191-8/+8
| | | | | | | | | | | | backslashes. They are still odd, though. For example, Paths are printed on Win32 as below; /tmp/dbginfo\def2.cc:4:0 /tmp/dbginfo\include\decl2.h:1:0 /tmp/include\decl.h:5:0 llvm-svn: 160505
* Replace some explicit compare loops with std::equal.Benjamin Kramer2012-07-192-11/+2
| | | | | | No functionality change. llvm-svn: 160501
* [arm-fast-isel] Add support for vararg function calls.Jush Lu2012-07-193-32/+84
| | | | llvm-svn: 160500
* DebugInfo library: add support for fetching absolute paths to source filesAlexey Samsonov2012-07-1910-24/+69
| | | | | | | | (instead of basenames) from DWARF. Use this behavior in llvm-dwarfdump tool. Reviewed by Benjamin Kramer. llvm-svn: 160496
* Fixed few warnings.Galina Kistanova2012-07-193-4/+4
| | | | llvm-svn: 160493
* Remove tabs.Bill Wendling2012-07-191-85/+85
| | | | llvm-svn: 160483
* Remove tabs.Bill Wendling2012-07-192-4/+3
| | | | llvm-svn: 160482
* Remove tabs.Bill Wendling2012-07-191-15/+13
| | | | llvm-svn: 160480
* Remove tabs.Bill Wendling2012-07-193-8/+8
| | | | llvm-svn: 160479
* Tweak prose.Chad Rosier2012-07-191-1/+1
| | | | llvm-svn: 160478
* Remove tabs.Bill Wendling2012-07-1917-79/+79
| | | | llvm-svn: 160477
* Remove tabs.Bill Wendling2012-07-193-13/+13
| | | | llvm-svn: 160476
* Remove tabs.Bill Wendling2012-07-1910-32/+35
| | | | llvm-svn: 160475
* Remove tabs.Bill Wendling2012-07-192-4/+4
| | | | llvm-svn: 160473
* Remove tabs.Bill Wendling2012-07-194-57/+57
| | | | llvm-svn: 160472
* Remove tabs.Bill Wendling2012-07-183-3/+3
| | | | llvm-svn: 160471
* Move around some enum elements so that lastMRM corrects gets assigned 56, whichRichard Trieu2012-07-181-2/+2
| | | | | | | is one more that MRM_DF which is 55. Previously, it held value 45, the same as MRM_D0. llvm-svn: 160465
* TblGen: Tweak to pretty-print DAGISel.inc a bit better.Jim Grosbach2012-07-181-2/+2
| | | | llvm-svn: 160463
* Allow PointerIntPairs to be created from const void *.Jordan Rose2012-07-181-1/+12
| | | | | | | For a measure of safety, this conversion is only permitted if the stored pointer type can also be created from a const void *. llvm-svn: 160456
* X86: remove redundant cmp against zero.Manman Ren2012-07-183-15/+95
| | | | | | | | | Updated OptimizeCompare in peephole to remove redundant cmp against zero. We only remove Compare if CF and OF are not used. rdar://11855129 llvm-svn: 160454
* This patch fixes 8 out of 20 unexpected failures in "make check"Preston Gurd2012-07-1811-34/+74
| | | | | | | | | | | | | | | when run on an Intel Atom processor. The failures have arisen due to changes elsewhere in the trunk over the past 8 weeks or so. These failures were not detected by the Atom buildbot because the CPU on the Atom buildbot was not being detected as an Atom CPU. The fix for this problem is in Host.cpp and X86Subtarget.cpp, but shall remain commented out until the current set of Atom test failures are fixed. Patch by Andy Zhang and Tyler Nowicki! llvm-svn: 160451
* Adding some debug information to PassManagerVictor Oliveira2012-07-181-0/+20
| | | | llvm-svn: 160446
* Whitespace.Chad Rosier2012-07-181-18/+14
| | | | llvm-svn: 160445
* Fix a somewhat nasty crasher in PR13378. This crashes inside ofChandler Carruth2012-07-182-22/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LiveIntervals due to the two-addr pass generating bogus MI code. The crux of the issue was a loop nesting problem. The intent of the code which attempts to transform instructions before converting them to two-addr form is to defer and reprocess any transformed instructions as the second processing is likely to have more opportunities to coalesce copies, etc. Unfortunately, there was one section of processing that was not deferred -- the INSERT_SUBREG rewriting. Due to quirks of how this rewriting proceeded, not only did it occur early, it removed the bits of information needed for the deferred processing to correctly generate the necessary two address form (specifically inserting a copy), but didn't trigger any immediate assertions and produced what appeared to be already valid two-address from code. Thus, the assertion only fired much later in the pipeline. The fix is to hoist the transformation logic up layer to where it can more firmly defer all further processing, and to teach the normal processing to handle an edge case previously handled as part of the transformation logic. This edge case (already matched tied register operands) needs to *not* defer any steps. As has been brought up repeatedly in the process: wow does this code need refactoring. I *may* squeeze in some time to at least bring sanity to this loop... but wow... =] Thanks to Jakob for helpful hints on the way here, and the review. llvm-svn: 160443
* Fix ARMTargetLowering::isLegalAddImmediate to consider thumb encodings.Andrew Trick2012-07-181-4/+11
| | | | | | Based on Evan's suggestion without a commitable test. llvm-svn: 160441
* whitespaceAndrew Trick2012-07-181-2/+2
| | | | llvm-svn: 160440
* Added unit test for PR13361: LSR + SCEV "hangs" on reasonably sized test.Andrew Trick2012-07-181-0/+517
| | | | llvm-svn: 160439
* test commitVictor Oliveira2012-07-181-0/+1
| | | | llvm-svn: 160438
* Add some missed ELF constants definitions:Simon Atanasyan2012-07-181-1/+36
| | | | | | | | | | - section types - dynamic table entries tags - state flags for DT_FLAGS_1 entry The patch reviewed by Rafael Espindola. llvm-svn: 160433
* Update config.h.cmake corresponding to config.h.in.NAKAMURA Takumi2012-07-181-7/+13
| | | | llvm-svn: 160431
* The vbroadcast family of instructions has 'fallback patterns' in case where theNadav Rotem2012-07-181-6/+8
| | | | | | | | | | | | load source operand is used by multiple nodes. The v2i64 broadcast was emulated by shuffling the two lower i32 elements to the upper two. We had a bug in the immediate used for the broadcast. Replacing 0 to 0x44. 0x44 means [01|00|01|00] which corresponds to the correct lane. Patch by Michael Kuperstein. llvm-svn: 160430
* Mips specific inline asm operand modifier 'M':Jack Carter2012-07-182-65/+131
| | | | | | | | | | | | | | | | | | | | | | Print the high order register of a double word register operand. In 32 bit mode, a 64 bit double word integer will be represented by 2 32 bit registers. This modifier causes the high order register to be used in the asm expression. It is useful if you are using doubles in assembler and continue to control register to variable relationships. This patch also fixes a related bug in a previous patch: case 'D': // Second part of a double word register operand case 'L': // Low order register of a double word register operand case 'M': // High order register of a double word register operand I got 'D' and 'M' confused. The second part of a double word operand will only match 'M' for one of the endianesses. I had 'L' and 'D' be the opposite twins when 'L' and 'M' are. llvm-svn: 160429
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