| Commit message (Collapse) | Author | Age | Files | Lines |
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vector elements.
llvm-svn: 155742
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x == -y --> x+y == 0
x != -y --> x+y != 0
On x86, the generated code goes from
negl %esi
cmpl %esi, %edi
je .LBB0_2
to
addl %esi, %edi
je .L4
This case is correctly handled for ARM with "cmn".
Patch by Manman Ren.
rdar://11245199
PR12545
llvm-svn: 155739
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llvm-svn: 155735
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llvm-svn: 155733
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llvm-svn: 155732
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Target specific types should not be vectorized. As a practical matter,
these types are already register matched (at least in the x86 case),
and codegen does not always work correctly (at least in the ppc case,
and this is not worth fixing because ppc_fp128 is currently broken and
will probably go away soon).
llvm-svn: 155729
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llvm-svn: 155727
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llvm-svn: 155726
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llvm-svn: 155725
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<rdar://problem/11325085>.
llvm-svn: 155724
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The limit is set to an arbitrary 1000 recursion depth to avoid stack overflow
issues. <rdar://problem/11286839>.
llvm-svn: 155722
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properly with how the code handles all-undef PHI nodes.
llvm-svn: 155721
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llvm-svn: 155720
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llvm-svn: 155716
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llvm-svn: 155706
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llvm-svn: 155705
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pre-pentiumpro architectures.
* Model FPSW (the FPU status word) as a register.
* Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions.
* During Legalize/Lowering, build a node sequence to transfer the comparison
result from FPSW into EFLAGS. If you're wondering about the right-shift: That's
an implicit sub-register extraction (%ax -> %ah) which is handled later on by
the instruction selector.
Fixes PR6679. Patch by Christoph Erhardt!
llvm-svn: 155704
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This change replaces projects/sample/autoconf/config.sub with a copy of
autoconf/config.sub.
llvm-svn: 155703
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llvm-svn: 155701
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the mask operand in the MCInst.
llvm-svn: 155700
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vectors"
It broke stage2 build. stage1/clang sometimes crashed.
llvm-svn: 155699
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llvm-svn: 155698
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Bridge after r155618.
llvm-svn: 155696
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llvm-svn: 155686
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instructions.
- However, it does support dmb, dsb, isb, mrs, and msr.
rdar://11331541
llvm-svn: 155685
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instead of getAggregateElement. This has the advantage of being
more consistent and allowing higher-level constant folding to
procede even if an inner extract element cannot be folded.
Make ConstantFoldInstruction call ConstantFoldConstantExpression
on the instruction's operands, making it more consistent with
ConstantFoldConstantExpression itself. This makes sure that
ConstantExprs get TargetData-aware folding before being handed
off as operands for further folding.
This causes more expressions to be folded, but due to a known
shortcoming in constant folding, this currently has the side effect
of stripping a few more nuw and inbounds flags in the non-targetdata
side of constant-fold-gep.ll. This is mostly harmless.
This fixes rdar://11324230.
llvm-svn: 155682
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The required checks are moved to ChainInstruction() itself and the
policy decisions are moved to IVChain::isProfitableInc().
Also cache the ExprBase in IVChain to avoid frequent recomputations.
No functional change intended.
llvm-svn: 155676
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No functional change intended.
llvm-svn: 155675
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(x & y) | (x ^ y) -> x | y
(x & y) + (x ^ y) -> x | y
Patch by Manman Ren.
rdar://10770603
llvm-svn: 155674
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analyzer. rdar://11329354
llvm-svn: 155669
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DAGCombine strangeness may result in multiple loads from the same
offset. They both may try to glue themselves to another load. We could
insist that the redundant loads glue themselves to each other, but the
beter fix is to bail out from bad gluing at the time we detect it.
Fixes rdar://11314175: BuildSchedUnits assert.
llvm-svn: 155668
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llvm-svn: 155661
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The base address for the PC-relative load is Align(PC,4), so it's the
address of the word containing the 16-bit instruction, not the address
of the instruction itself. Ugh.
rdar://11314619
llvm-svn: 155659
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llvm-svn: 155657
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the FeatureLeaForSP feature bit when llvm auto detects Intel Atom.
Patch by Andy Zhang
llvm-svn: 155655
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While making lld build under the tools directory I decided to refactor how this
works.
There is now a macro, add_llvm_external_project, which takes the name of the
expected subdirectory. This sets up two CMake options.
* LLVM_EXTERNAL_${NAME}_SOURCE_DIR
This is the path to the source. It defaults to
${CMAKE_CURRENT_SOURCE_DIR}/${name}.
* LLVM_EXTERNAL_${NAME}_BUILD
Enable and disable building the tool as part of LLVM.
I chose LLVM_EXTERNAL_${NAME} as a prefix so they all show up together in the
GUI.
llvm-svn: 155654
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'REPLACEMENT CHARACTER' (U+FFFD) when getAsInteger fails.
llvm-svn: 155653
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checking the increment for big mode, we can only check that all items are in map.
llvm-svn: 155651
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On some cores it's a bad idea for performance to mix VFP and NEON instructions
and since these patterns are NEON anyway, the NEON load should be used.
llvm-svn: 155630
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llvm-svn: 155626
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corei7-avx, core-avx-i, and core-avx2 cpu names.
llvm-svn: 155618
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elements to minimize the number of multiplies required to compute the
final result. This uses a heuristic to attempt to form near-optimal
binary exponentiation-style multiply chains. While there are some cases
it misses, it seems to at least a decent job on a very diverse range of
inputs.
Initial benchmarks show no interesting regressions, and an 8%
improvement on SPASS. Let me know if any other interesting results (in
either direction) crop up!
Credit to Richard Smith for the core algorithm, and helping code the
patch itself.
llvm-svn: 155616
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llvm-svn: 155604
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the feature set of v7a. This comes about if the user specifies something like
-arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as
uxtab in this case.
rdar://11318438
llvm-svn: 155601
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MDNodeOperand value.
llvm-svn: 155599
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llvm-svn: 155589
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a failure if run on an Intel Atom with post RA instruction scheduling.
llvm-svn: 155587
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Comparing ~0UL with an unsigned will always return false when long is 64 bits long.
llvm-svn: 155568
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llvm-svn: 155567
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llvm-svn: 155566
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